Part Number: TPS54394 Minimum Vin1 and Vin2 for TPS54394 for output of 1.1V on VOUT1 and 3.3V on VOUT2.
I am designing this regulator with the input range of 4.5V to 16V (USB-C VBUS), and so I need the TPS54394 for output to be 1.1V on VOUT1 (worst case…
Part Number: TPS54394 It's funny on one thread regarding this part, someone said the user's layout was very bad because the switch node was connected to the inductor using a different layer. That is the (poorly) recommended layout on page 16 of the data…
Part Number: TPS54394 The datasheet for this part indicates a VIN range of 4.5 to 18V. The block diagram and text throughout the document show VIN1 feeding an internal 5V regulator. How is it supposed to regulate to 5V if the input is 4.5V?
Part Number: TPS54394 Hello,
I need to run a simulation of the using the TPS54394 to see if I can modify it correctly to power sequence in the correct order for an FPGA. Right now I'm just trying to get the model to run, and I more or less used the design…
Part Number: TPS54394 Hello,
I am working with TPS54394 and we are generating two 5V outputs from 12V input. In channel 1, the output ripple seems ok, however in channel 2 the ripple of 5V output is too high.
In both channels the average output value is 5V…
Part Number: TPS54394 Hi, There
We are using TPS54394 as our power solution:
1.CH1 is 3.3V@1.5A,and Cout is around 100uF;
2 CH2 is 1.0V@2A, and Cout=660uF according to FPGA requirment.
3. Vin=12V ,Vinmax=14V
Per TPS54394's spec, Cout range is 22-68uF…
Part Number: TPS54394 Other Parts Discussed in Thread: TINA-TI , Hi I would like to ask for the TPS54394 transient spice model to be used on the Tina-Ti tool. Thanks in advance.
Part Number: TPS54394 Hi Team,
My customer is using TPS54394 to power the Core Voltage of FPGA. And they put 10*100uf capacitors at the input of FPGA which becomes the output capacitors of TPS54394. I wondering if it is ok? if not, do you have any other…
Part Number: TPS54394 Hi,
Figure 27 of the TPS54394 datasheet, there are these recommendations: a. Keep vias > 3-4 mm from input capacitors b. Keep vias > 3-4 mm from output capacitors c. Keep output vias > 25 mm from input vias What is the purpose…