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  • TPS650864: Powering GTR rails with the TPS650864

    Part Number: TPS650864 I am developing a PDN for a Xilinx Zynq UltraScale+ XCZU7CG FPGA. The TPS658640 PMIC looks like a good fit, but the corresponding block diagram in the TPS650864 datasheet (Figure 7-3) does not include the GTR rails. Is there a…

  • TPS650864: TPS650864---Abnormal voltage output issue

    Part Number: TPS650864 Dear engineers, hello everyone! We have encountered some issues when using the TPS650864, and we would appreciate your help in analyzing them. Thank you. Currently, CTL1\4\5 are pulled high, and we are not using I2C for configuration…

  • TPS650864: How to select Inductor and output cap value for controllers in tps650864

    Part Number: TPS650864 Other Parts Discussed in Thread: TIDA-01393 , CSD87381P I am designing a PMIC for the Zynq UltraScale+ MPSoC XCZU11EG, and I am confused about calculating the inductor, RILIM, and output capacitor values for BUCK1, BUCK2, and BUCK6…

  • TPS650864: TPS6508641RSKT Power-Up and Output Voltage Issue

    Part Number: TPS650864 Dear Team, We are using TPS6508641RSKT in one of our design with XCZU3CG-L1SFVC784I. The input for TPS6508641RSKT is 6V, Buck 1 is configured for 5V, Buck 2 as 0.85V. The output of Buck 1 will be my input to Buck 3,4 & 5. We are…
    • Answered

  • TPS650864: The GPO3 behavior of TPS6508641

    Resolved
    Part Number: TPS650864 Hi, I want to know if the GPO3 will reflect the power good state of all previous rails or it will simply reflect the state of CTL1. And toggling of CTL1 in the powering up sequence will affect the sequence or not? Thanks.
    • Resolved
    • Answered

  • TPS650864: How to insert the VCCINT_VCU rail?

    Resolved
    Part Number: TPS650864 Hi, In scea113, it suggests to use an extra buck converter to power the VCCINT_VCU rail. Per the AMD's DS, the recommended power sequence is: VCCINT -> VCCINT_VCU -> VCCAUX, this means the best point is after the GPO4 high but…
    • Resolved
    • Answered

  • TPS650864: The usage of CTL3 and CTL5

    Resolved
    Part Number: TPS650864 Hi, The chip claimed support the 'full power domain flexibility power modes'. The CTL3 (PS_FP_PWR_EN_LS) and CTL5 (PL_PWR_EN) seems designed to connect to PMU's GOP1[0] and GPO1[1] in Zynq MSop+, right?
    • Resolved
    • Answered

  • TPS650864: Will LDOA1 (VPS_MGTRAVTT) wait on CTL5 (PL_PWR_EN)  ?

    Resolved
    Part Number: TPS650864 Hi, For TPS6508641, the Figure 7-11 shows LDOA1 ramping up after CTL5, if this imply once we close the PL power, the PS side GTR will be disabled too? Thanks
    • Resolved

  • TPS650864: Re-boot issue due to unused LDOA3 on TPS650864

    TI Thinks Resolved
    Part Number: TPS650864 Other Parts Discussed in Thread: TPS650861 Tool/software: Hi Team, We have design a custom design using the Zynq MPSoC and TPS6508641RSKT PMIC, in which the LDOA3 output is unused and connected with a 4.7 µF output capacitor.…
    • Answered

  • TPS650864: TPS65086401 Power Good

    Resolved
    Part Number: TPS650864 Hi team, Regarding the TPS65086401, is my understanding correct that GPO3 does not output a logic high when BUCK4 and the VTT LDO become stable, but is simply a pin that goes high 5 ms after GPO1 rises? Best Regards, Shot…
    • Resolved

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