Hi Stephen,
you summarised it correctly, I want to add a point, the Connectors are mounted at Panel.
There is no direct noisy signal set under the LDO area. No other signal present.
FB pin placed at top layer, ( Layer2 and Layer3 are empty under FB pin…
Hello Fabien,
Unable to view any PCB layout, but your description leads me to believe that it would be adequate.
The number of variables to sometimes cause an unexpected increased temperature is limited.
Since the silicon die is attached directly (i.e…