Part Number: TSW54J60EVM Other Parts Discussed in Thread: ADS54J60 , , LMH6401 Hello,
We are using TSW54J60EVM (ADC chip: ADS54J60) with a Xilinx FPGA to build a high speed data acquisition system. So far, we got the ADC and data communication (JESD204B…
Part Number: TSW54J60EVM Other Parts Discussed in Thread: ADS54J60 , TI-JESD204-IP Hello,
I am using the TSW54J60EVM and a Avnet FPGA development board for a high speed ADC data acquisition system. I set up the ADC/PLL parameters using TI's ADC54JXXEVM…
Part Number: TSW54J60EVM Other Parts Discussed in Thread: ADS54J60 Greetings,
As a student, I am looking for a RF signal capturing board. In this data capturing process, I will be capturing transient signals. I need to ask following questions for my study…
Part Number: TSW54J60EVM Other Parts Discussed in Thread: LMK04828 , ADS54J60 , Hello, The datasheet of TI ADS54J60 ADC chip, page 6, says that, pin 28 and 27, clock inputs, CLKIN[M,P], have an internal 100 ohm termination. But in its Evaluation Module TSW54J60EVM…
Part Number: TSW54J60EVM Other Parts Discussed in Thread: ADS54J60 Hi,
I'm currently using 8-2-2-4 mode with the attached configuration setting and would like some help addressing two questions.
1. Is my configuration setting right for 8-2-2-4? I'm…
Part Number: TSW54J60EVM Other Parts Discussed in Thread: TSW14J57EVM , TSW14J10EVM , ADS54J60EVM , LMK04828 , ADS54J60 Hello! I need to configure the TSW54J60EVM board using the ADS54Jxx GUI v1.8 so that the sampling rate would be 1 GSPS. As far as I understand…
Part Number: TSW54J60EVM Other Parts Discussed in Thread: ADS54J60 , LMH3401 , LMH5401 Hello,
I noticed that you swapped OUT+ and OUT- on the LMH3401 after the filter. OUT+ goes to AINM and OUT- goes to AINP. It looks like you did this for layout purposes…
Part Number: TSW14J56EVM Hi Team,
I received the following request, can you help me?
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I need a digitizer to collect RF signals. From Texas Instrument (TI) website, I found a “digitizer” board (TSW54J60EVM…
Part Number: TSW54J60EVM Hello,
I am using ti FPGA firmware with a xilinx FPGA board.
I sometimes see JESD interface error (about one in three power cycles of the FPGA board).
Any reason behind this behavior?
Also, if I reprogram the TSW54J60 board, then…