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  • ADC32RF55: SYSREF timing

    TI Thinks Resolved
    Part Number: ADC32RF55 Other Parts Discussed in Thread: ADC12DJ2700 , LMK04832 Tool/software: Dear Person in Charge, I am going to make a board using ADC32RF55 and evaluate its performance. I have a question about the timing of SYSREF and device clock…

  • ADC09QJ1300: interleave channels on ADC09xJ1300 series ADC

    TI Thinks Resolved
    Part Number: ADC09QJ1300 Other Parts Discussed in Thread: ADC09DJ1300 , ADC12DJ2700 Hello guys, I've been reading the datasheet of ADC09xJ1300 series ADCs, I wonder if it's possible to interleave multiple channels on a single chip to achieve a higher…
    • Answered

  • XAD12DJ135 documentation

    Resolved
    Other Parts Discussed in Thread: ADC12DJ1350 , ADC12DJ2700 , ADC08DJ3200 , ADC12DJ5200RF , ADC12DJ3200 Hello, can we assume that the part marked as XAD12DJ135 is an ADC12DJ1350, which is mentioned only once in this forum and nowhere else? Thus falling…
    • Resolved
    • Answered

  • ADC12DJ2700EVM: Set up for DC coupled Input

    Resolved
    Part Number: ADC12DJ2700EVM Other Parts Discussed in Thread: ADC12DJ2700 Hello team, Customer needs to evaluate ADC12DJ2700 for their application with a DC coupled input. I see the EVM has a transformer and supports 500kHz-9GHz inputs. Do we have a…
    • Resolved

  • ADC12DJ5200RF: Looking for the .bxl file

    TI Thinks Resolved
    Part Number: ADC12DJ5200RF Other Parts Discussed in Thread: ADC12DJ3200 , ADC12DJ2700 Hi, Good day. Our customer was looking for the .bxl file for TI P/N ADC12DJ5200RF. I check it in the product folder but it is unavailable. Also, we check the ADC12DJ3200…
    • Answered

  • RE: ADC12D1800RFRB: Interface to Computer

    Resolved
    Hi Matthew I agree that using one of our ADC EVMs and an FPGA development board might be a better solution to your needs. The ADC12DJ3200 is a 12 bit ADC that can operate at up to 6.4GSPS in single input mode, or 3.2 GSPS in dual input mode. A slower…
    • Answered

  • RE: ADC12DJ3200: SRC_DONE bit

    Resolved
    Hi Hiroshi, Yes your assumption is correct SRC_DONE bit is only set(set to '1') if the calibration was successful. Regards, Neeraj

  • RE: ADC12DJ3200: ADC Ramp Test Pattern

    Hi New2day, Section 7.4.5.3 Ramp test Mode of the datasheet explains your question in detail. Here is the info. In the ramp test mode, the JESD204B link layer operates normally, but the transport layer is disabled and the input from the formatter…

  • RE: ADC12DJ3200: S-parameter

    Hi Lilian Here is SDD11 data (input return loss data for the differential analog input port) based on the earlier .s2p file. /cfs-file/__key/communityserver-discussions-components-files/73/1348.ADC12DJ2700_5F00_TRMCalibration_5F00_Sdd11_5F00_031716…
    • Answered

  • RE: ADC12DJ3200EVM: ADC12DJ3200

    Resolved
    Jimmy, The schematic is attached. FYI, you can download the entire board design package including the schematic under the ADC12DJ3200EVM product folder on the TI website. Regards, Jim 6874.ADC12DJ3200_HSP001EVM-SCH_A.pdf

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