Hello Mustafa,
A few notes first off these results can be a little misleading because you are not capturing a coherent fft signal, to do this you can do one of two things either adjust the input frequency based on the number of samples you are capturing…
Part Number: ADC12DJ3200 Hi Team,
What are the expected voltage levels when the TMSTP_LVPECL_EN is set to '1' ?
Can you tell me how the voltages of LVPECL fit with the requirement for common mode
please refer to section 6.3 - Recommended Operation…
Hi,
Sorry for late to reply. I miss some mail noticification.
Got it! Thanks!
Can i deliver a clock signal with 3.2GHz to ADC12DJ3200's CLK+/- pins directly? As we know, the ADC12DJ3200 support maximu clk input up to 3200M.
Thanks!
Lyndon
Part Number: ADC12DJ3200 Other Parts Discussed in Thread: AFE7950 Hi,
1.Any Transceiver IC support up to 3GHz range in TI?
else
2.How to interface ADC12DJ3200 with msp430?
Thanking You.....!
Hello,
Can you clarify I am not exactly sure what you mean by the clock is recovered from the transceiver, if you are using the EVM the ref clock should be coming from the EVM.
Thanks,
Eric
Hi Cherry,
Here are the updated register writes.
SCR_Done does not complete means the sysref is not getting calibrated properly. Can you please make sure the sysref is getting to the ADC?
Regards,
Neeraj
Part Number: ADC12DJ3200
Hello,
Our customer used his own ADC12DJ3200 board, 2.4Gbps sampling rate, MODE3,16lane,dual-channel mode, input 264Mhz, -1dBFS single frequency signal, signal source output added low pass filter inhibit harmonics, sample analysis…
Part Number: ADC12DJ3200 Other Parts Discussed in Thread: LMK04828 , , TSW14J57EVM Hi team,
The ADC model is ADC12DJ3200 and the PLL is LMK04828.
The ADC sampling rate is 5 GSPS, the sampling clock provides 2.5 GSPS, and the sysref is 3.90625 MHz, in pulse…