Part Number: ADS54J60 Dear Amit,
Now, we are able to capture the Pulse signal on HSDC pro with the help of BD design project shared by you. But this is working fine for pulse (Pulse width : 20 ns) with frequency above1 MHz signals due to high value of core…
Part Number: ADS54J60EVM Other Parts Discussed in Thread: ADS54J60 Hi,
I will use ZCU102 evaluation board with ADS54J60EVM. I intend to use the ip core JESD204 from the xilinx vivado software. Can I use IP Core JESD204B from the supplier xilinx and not…
Part Number: ADS54J60 Hello
We assembled the ADS54J60IRMP (VQFNP72 package) on my PCB in an automatic machine and we got an error in our tests, After we soldering the legs of the component manually, the problem was solved
Are there any special instructions…
Part Number: ADS54J60
Hello. Tell me about the ADS54J60 built-in SerDes PLL 1. How long is the PLL reset time? (Write 40h to address 6-017h. -> Write 00h to address 6-017h. Time for this period) 2. How long should I wait for the next setting after…
Part Number: ADS54J60 Hi team,
1) The ADS54J60 is configured to capture data and establish an 8224 link with JESD204B, strictly in the order of ADC hardware reset, SPI write, and JESD204B core reset. The link establishment should have been completed with…
Part Number: ADS54J60 Hi
I have following questions
1. If we use a single channel only with PDN MASK, can we set Open or NC (No Connect) for no use channel output pins? For instance, if we use Ch A only, can we set LMFS 8224, BBxM and DBxP Open?
2. What…
Part Number: ADS54J60EVM Other Parts Discussed in Thread: ADS54J60 , , DAC39J84 Hi,
I am working on deterministic latency design with ADS54J60 board, VC707 board, and Verilog code based on JESD204B reference design provided by TI.
I could get the sampled…
Doug,
I would suggest trying different values for the elastic buffer delay (RBD) in your FPGA JESD IP Core. You may also want to increase the K value as well to allow for more lane buffering. The buffer release point in your FPGA may have been right on…
Part Number: ADS54J60 Hello,
IL correction does not perform well, if a low DC offset is given in Signal or intermitting small signal and large signal.
We need to use frozen IL, DC coupling, random signal from customer, typ. 1Gsps.
Is there a possibility…