Part Number: LOWPASSFILTER-CALC Other Parts Discussed in Thread: LM6154 The Filter design tool:
It is not possible to lock a amplifier.
It takes a lot of time to set it back each time.
Bug: It is not possible to lock E24 resitor and capicitors. When a…
Part Number: AFE8000 For simulation requirements needs we should have the internal RX and TX filters structure as detailed below:
The DUC interpolation filters coefficient for the two next scenarios:
375[MSPS] input signal that interpolating to 12…
Part Number: ULC1001-DRV290XEVM Other Parts Discussed in Thread: DRV2901 , ULC1001 Hi~
Customer is under evaluating ULC1001-DRV290XEVM board and got several question as below.,
1. At DRV2901,how to boost output voltage? When see bootstrap, looks charge…
Hello Steve,
Would you mind filling out the calculator spreadsheet with your requirements and also share your schematic?
LM25088-5088QUICK-CALC Calculation tool | TI.com
There could be a number of reasons for instability.
1, Loop compensation
2. No…
Hi Ram,
Ram said: If I increase the Over Sampling Ratio to 512 (now I have it at 128), reducing the data rate to 8 ksps, could I have a higher cut-off freq for Sinc3?
My answer: the cut-off frequency of Sinc filter can be calculated as f-3db = data rate…
Hi
Here is the update from the developer post SDK9.1 testing
We tried reproducing this bug.but unable to do on the latest ti-rt-linux-kernel Once both interfaces (eth1 and eth3) are synchronized using phc2sys. And PPS signal is generated. We see the LEDs…
Hi Mani,
Optionally as well, At the output you can implement an LC filter with a cutoff frequency of 20kHz to attenuate switching and cut high frequency noise. You can use this calculator to determine component values ( https://www.ti.com/tool/LCFILTER…
Hi Liang
For audio, LC filter mostly check the frequency response results. You could follow below link to use the tool to check the results. And from experience, usually around 1uF is a good choice.
https://www.ti.com/tool/LCFILTER-CALC-TOOL
Hi Robert,
The test pattern, with digital bypass disabled, is expected to be used with the DDC. Without DDC enabled and appropriate settings configured, the test pattern will not output.
When digital bypass is disabled, the signal is routed through the…
Thank you for replying Rob,
I forgot to mention in my setup. I am using Rohde & Schwarz SMA 100 signal generators for clock and signal. For the clock my settings are 250MHz freq and 15 dBm level. For the signal I my settings are 100MHz freq and 9 dBm…