Part Number: ADS1675 Good afternoon,
We're looking at using the ADS1675 for our design but could not find a specification in the datasheet that shows the relationship between clock jitter tolerance and SNR. Are there additional resources that show…
Part Number: ADS131M04 Hello guys,
One of my customers is considering using ADS131M04 for their new products.
They want to use MSP430 clock output (8MHz) as ADS131M04 CLKIN. But the clockoutput has about +/-3% jitter.
So they want to know how much SNR…
Hi jito,
For an oversampling ADC such as the ADS131A04, the SNR impact due to jitter is given by the equation shown below
If you want to run the ADC at 128 kSPS, the dynamic range if 85.12 dB and the OSR = 32. The 3dB BW is given by the plot shown below…
Hello Preethi, Can you quantify your design requirements if possible? Do you value in band or device noise floor? Do you have a certain RMS jitter requirement over a defined integration band/ You mention good phase margin margin, what is your requirement…
Part Number: ADC12DJ3200QML-SP Hi Team, We have a customer inquiry regarding figure 28 on page 29 of ADC12DJ3200QML-SP datasheet. 1. SNR is dependent on clock jitter. These are the measured results. 2. Do you know what the clock jitter is in these measurements…
Part Number: ADS5474 Hi,
In the datasheed for ADS5474 the figure 45 shows SNR vs Input Frequency and External Clock Jitter with measurements up to 200-fs jitter.
How can user estimate SNR degradation if the jitter is up to 850-fs?
Thanks.
Theoretically SNR should be approximately 6.02*N and should not change with input frequency. However sometimes clock Jitter during measurement may lead to a change in the noise level.
What equipment are you using to do the test?
Hi Steve,
For a DC measurement, the jitter of the clock does not impact noise at all! However, there is always some upper frequency of interest that is non-zero.
This TI Precision Labs presentation provides some details on the calculation of jitter based…