Part Number: ADS5294 Other Parts Discussed in Thread: LMK04826 I am aware of the relationship between sample clock jitter and SNR. If I am using a clock generator device, what I am unclear about is which of the jitter specifications I should be using…
Hello Raneel,
We do not recommend to characterize eye diagram/jitter for 953 since the only way that can be done is without the deserializer attached. When the deserializer is not attached, the SNR is not representative of what it would be in the actual…
Part Number: ADS9817 Hi all,
What is the minimum amplitude width specification, like the minimum VID for the SMPL_CLKP and SMPL_CLKM pins during differential input? The data sheet also states the following:
"Clock amplitude impacts the ADC aperture jitter…
Part Number: ADC12QJ1600-SP The ADC datasheet says that "TI Strongly Recommends that CLK± be AC-coupled with DEVCLK_LVPECL_EN set to 0 to allow CLK± to self-bias to the optimal input common-mode voltage for best performance." Thus…
Part Number: PCM1794A What is the max jitter specification required on SCK3 in order to meet the specified SNR (say -125dB @ 17kHz)?
For example, with a 48kHZ sample clock (SCLK3 = 18.432MHz, 384Fs) and an output frequency we calculate the jitter needed…
Hello Liping,
1) In datasheet, it defines 25.6MHz is typical clock input. So I use 24MHz should be fine, right?
Yes, 24MHz will work well; this is the default frequency used on the ADS127L11 evaluation board. Note that all data rates will scale with the…
Part Number: TAS5828M Other Parts Discussed in Thread: SRC4192 I have a question about the TAS5828M sample rate converter performance. The data sheet does not provide too many details regarding sample rate converter performance.
I have an application…
Hi Matteo,
Oh yes, good catch - you are correct. I used the NSD value for the ADC3561 (-150 dBFS/Hz). Yes please substitute the -158 dBFS/Hz for the ADC3563 into the equation.
I did a search with these parameters on our device page. I had to back calculate…
Part Number: ADS4449 Other Parts Discussed in Thread: ADC08D1520 , How can I determine the maximum amount of jitter tolerable from my clock source? The datasheet just says to use a very low jitter clock source. I've looked at the ADC08D1520 which gives…
Hi Yuan,
The ADC jitter requirement can be found on page 47 of the datasheet (8.3.2.2 SNR and Clock Jitter). If you look at Figure 8-7, you can see how SNR degrades over input frequency due to external clock jitter. If you want the device to perform in…