Hi Board designers,
Refer below inputs for the OLDI interface related queries.
Supported display configurations.
Does AM62xx support 4 lane or 8 lane or both 4/8 lane type of LCD displays.
The AM62x OLDI support 1 X 8 lane (dual link mode) and 2 X 4 lane…
Part Number: DS90UB949-Q1 Hello team, I am using a DS90UB949-Q1-based EVK kit for my test. My setup is such that, I have a device present at the Deser (UB948) side which is connected to the Deser using I2C and a GPIO pin is also input to the Deser. The…
Part Number: LMK04828 Other Parts Discussed in Thread: LMK04832 Hello,
We are working on the xilinx based RFSoC application Design and planning to use LMK04828B for reference clock
As per our understanding from the LMK04828B datasheet, the output clock…
Hi IK
Sorry, pressed send before I finished the last post,
I was wondering if above calculations are correct? My LVDS screen max clock frequency is 50MHz and we are using 16bpp for now.
For debug external REFCLK can I use the CDCEL913PW exactly as shown…
Part Number: HD3SS3411 Hi,
Is it possible with HD3SS3411 (One Channel Differential 2:1 Mux/Demux) to make a MUX / DEMUX toplology as per the attached diagram? We have A and B channel of LVDS ( Asynchronous, Direct coupling ( No AC caps), VCM=1.25V, VDIFF…
Part Number: TMUXHS4212 Other Parts Discussed in Thread: HD3SS3212 Hi,
We have a system where we have to connect a ZynQ ultrasclae EVK to 6 nos of Spartan 6 FPGA through asynchronous LVDS (Tx&Rx) running at 100 Mbps (50MHz), DC coupling mode ( no…
I was wandering if it was possible to have the layout files from LVDS-18B-EVK. Any Ti employee that can answer this question? That could really be helpfull, since the ev kit is working fine, in my lab.
Thank you, Savino
Hi Jackson,
Thanks for your reply.
If you can run this code and flash to the EVM system with no problems, then it seems that a difference between this and your customer HW might be an issue. Are there any major differences in the HW setup?
=====the…
Part Number: DS90LV027A Hi,
We are facing some Voltage Level issue with LVDS. In our case we have to setup an LVDS communication with an FPGA EVK to our DUT. DUT LVDS line is 2.5V. The FPGA pins which is available in FMC connectors is at 1.2V level. So…