Kennon
Sorry for the delay on this issue, I checked with the design team and we still wants the HDP_SNK to be hold low even with VDD powers up before VCC.
Thanks
David
Part Number: SN75DP130 Other Parts Discussed in Thread: SN65DP141 , TDP142 We will be launching a board redesign to eliminate the DP130. Which component do you recommend we implement as the replacement for the SN75DP130?
Part Number: SN75DP130 Other Parts Discussed in Thread: TUSB1064 , , TUSB564 hi,
My customer use TUSB1064 for type C alternate mode.
for display port, they only need 5.4G. But the distance between TUSB1064 and scalar is more than 32cm.
They are afraid that…
Part Number: SN75DP130 hi,
Can i get any IC which has similar properties of SN75DP130 with operating temperature of -40 to 85 C.
I need a redriver which converts dual mode display to dp or hdmi in industrial operating temperature range.
Please help. …
Part Number: SN75DP130
This is a continuation of #CS0522713 that was initiated by our contract manufacturer but that thread has been locked by TI and our contract manufacturer has requested help in solving the problem from us (the designers/owners of…
Part Number: SN75DP130 Dear Expert
1.This is our topology ,could it be work?
2.Could you help to check this shcmetic , I found that some time have splash screen problem.
Part Number: SN75DP130
Hi Team,
We' using SN75DP130 and ITE factory debug found that the eye diagram of the DP130 output is unbalanced for 4 lanes, they are targeting lane0 for other lanes.
Eyes figures are as shown in two screenshot below.
Lane0…
Part Number: SN75DP130 Defect:DP2DATA_RD voltage output high(1.1V),the normal output is 0.8V
Failure rate is 10%.
We did ABA cross check.
Number: CS0522713
Hi,
DP130 will just pass on the EDID AUX Read command from the output board card FPGA to the input board card.
If you put the logic analyzer between the output board card FPGA and DP130, are you able to see the EDID AUX read command being sent by the…