Part Number: ADC3422 Hi Team,
Good day! Our customer is asking how ADC3422 can be interface with a spartan 6 FPGA. If possible could you please provide Verilog files or some project for ADC3422?
Thank you so much in advance.
Best regards,
Jonathan
Part Number: SPARTAN-6-LX150T-REF Hi,
I'd like to ask quote for 1 of Spartan-6 LX150T Dev Kit.
Your site shown me it's active part.
Could you please advise me How can I buy this part?
Spartan-6 LX150T Dev Kit
Part Number: SPARTAN-6-LX150T-REF Hello!
I did not find any information in user guide about configuration Ethernet PHY on the board LX-150T to using MII interface which supporting by IC DP83865. Schematic of this board will be very helpful, but I can't…
Part Number: TPS51200
Hi,
Could you let me know availability of below usage?
VTT --> 6 DDR4 ICs
REFOUT --> REF of 6 DDR4 ICs
How many DDR4 componet can TPS51200 support?
Thanks.
Part Number: TXB0108 Other Parts Discussed in Thread: SN74LVC4245A , ALLIGATOR , SN74LVC8T245 Hi there,
I am currently trying to drive a 2.5 MHz square wave through the TXB0108 device. I believe there is a problem in the matching of the line/termination…
The 5V tolerant (Open Drain) pins are PA0/1. These pins have no Analog function [Ref datasheet (SLASEX5A) Table 6-1].
This is also true in the G series and the C series. The TRM(s) don't say (one way or the other) whether there's a design-level conflict…
Part Number: AFE7906 Hi,
Greetings!
We are planning to integrate four AFE7906 with AMD's versal premium VP2802 SoC with the following configuration.
Sampling Rate: upto 3GSPS
Number of channels: 6
Bandwidth Required: 500Mhz.
In VP2802 SoC, I am planning…
Hi Simon,
The input current on the reference pin is listed on the DS (about 650us on the fastest version). The circuit to drive the REF would be something like what is described on the figure 6 of the DS.
Nevertheless, I'm far from an expert on power…
Part Number: ADS5282
I am working on a project that involves SP605 xilinx eval board and an ADS54RF63EVM ADC eval module (along with the ADC to FMC passive adapter board). I'd like to capture ADC output and send it out of the gigabit ethernet interface…
Hi Andrea,
Yes, I'm using dual loop nested 0-delay mode and I'm using external VCXO for PLL1 and embedded VCO0 for PLL2.
1. When I wrote " Use single ended SYNC/SYREF input" I meant connecting the positive line of my incoming differential…