The allowed inductance (and its range) is shown in Table 3.
What is your ripple target/spec? This reference design shows the common way to get low ripple, with an LDO after the DC/DC: http://www.ti.com/tool/TIDA-01566
As well, make sure you check…
Thanks for posting your ripple requirement. It is nearly impossible to get below 1 mV ripple while maintaining low Iq (operating in PFM).
So, we made this reference design last year to show how to achieve this: www.ti.com/.../TIDA-0156…
No, we don't have this data already. You can contact me and we can discuss the specific needs of your customer.
TPS82671 should be lower noise as it has higher Iq and supports the lower noise forced PWM mode.
There is also this TI Design…
Normally, customers would drive the MODE pin high with a GPIO. But it sounds like you want forced PWM mode all the time?
Alternatively, here's an approach that achieves low noise and good efficiency: www.ti.com/.../tida-01566