Part Number: TPS3430 Hi team,
we had integrated tps3430 WWDOG timer, based on configuration:
and calculated tWDU=62.74ms, tWDL=7ms and tRST=0.70ms.
I'm implementing code in such a wat that after enabling WDOG using SETx pins(only possible condition…
Part Number: TPS3430 Hi team,
My customer has two questions regarding TPS3430, can you help advise?
1. In the datasheet, it shows that,
To achieve the latching watchdog feature, an open-drain buffer is connected from WDO to CRST with a small value capacitor…
Part Number: TPS3430 the datasheet states "WDO delay time can be set to any value between 700 μs (CCRST = 100 pF) and 3.2 seconds (CCRST = 1 μF)"
I need at least 5s for reset. Is it really not possible to use a 2.2uF cap in CCRST?
tha…
Part Number: TPS3430-Q1 Other Parts Discussed in Thread: TPS3430 , Hi, Support Team
TPS3430_LHM_WDI have 3.3v, LHM_WDO_OUT will keep low.
if TPS3430_LHM_WDI dont have 3.3v, LHM_WDO_OUT will turn to Hign
schematic as below chart: have any concern?
also…
Part Number: TPS3430 We are using TPS3430 watchdog timer which is connected to the SoC. The input for the watchdog timer would be a pulse signal. Is there any sample code/library file that can be used in the SoC, so that the tps3430 can get the input…
Part Number: TPS3430 Dear TI support,
I'd need to know what is correct sequence for SET0, SET1 signals if I switch between WD disabled (SET0 = 1, SET1 = 0) and 9ms / 195ms setting (SET0 = 0, SET1 = 1). So it requires changing both signals. Can I switch…
Part Number: TPS3430-Q1 Hello team,
Can you reply the following questions of TPS3430-Q1?
-. When TPS3430-Q1 is always powered on in the MCU’s sleep mode which can’t give WDI, does the RESET (WDO) by TPS3430-Q1 watchdog continue to operate?…
Part Number: TPS3430-Q1 Hello TI-Team,
I use the TPS3430-Q1 in a safety project and i would like to know the resistance of the Open-drain output WDO when it is asserted. I want to know the value to calculate the resulting voltage on the reset pin of the…