Part Number: DAC39J84EVM Other Parts Discussed in Thread: ADC12DJ3200EVM , Hi All,
Hope you are doing great!!
We are generating constant amplitude square pulses from TSW14J56EVM using a .csv file (attached with the message) and sending it to DAC39J84EVM…
Archie,
For #1: See attached document.
For #2: The board is designed to use the HPC on the FPGA platforms.
For #3: You can use the source code that can be found under the TSW14J10EVM product folder (older Xilinx code that is not recommended) or…
Part Number: TIDA-01021 Other Parts Discussed in Thread: ADC12DJ3200EVM , TIDA-01022 , ADC12DJ3200 , TIDA-01023 , TIDA-01024 , ADC12J4000 , ADC12J4000EVM Hi,
My group at Lawrence Livermore National Laboratory, a research laboratory and not a company…
4375.SLAU580B.pdf Diverger,
The Xilinx firmware developed to be used with the TI ADC34J43EVM, a TSW14J10EVM, a Xilinx FPGA development board and the TI HSDC Pro GUI required a second clock (core clock). This clock was to be provided by the mezzanine…
ADC12J4000_DEC_10_VC707.pptx 7607.SLAU580B.pdf Ryuji,
We have tested the three boards in the past with no problems. See attached documents for more info.
Regards,
Jim
Imran,
I am not sure what a ZC702 board is but we have tested both our DAC38J84EVM and DAC38RF82EVM with a ZC706. We use a TSW14J10EVM, also from TI, to allow us to run our HSDC Pro GUI on the Xilinx platform. See the attached document for more information…
Zhipeng,
I was able to get the DAC running with no issues using numbers close to yours with a VC707 platform. See attached file for info regarding this. May you have to consult with Xilinx if you are still having problems. I have also attached another…
Harold,
What mode will you be using the ADC12J1600 in? I ask since the KC705 only has 4 JESD lanes routed and will not work if you are planning on using 8 lanes. Please see the attached TSW14J10EVM User's Guide for more information regarding using Xilinx…
Archie,
The flat line exists in both plots. You do not see it in the TI plot as the view is not zoomed in. This line is due to the default setting in the GUI to notch out 25 bins on both sides of the fundamental. See attached document for how to adjust…
