THS4631: Oscillation at low gain differential configuration

Going to need the load Catalin - if capacitive, might be the issue. 

The load is another THS4631 configured as differential amplifier and the connection is through 1kOhm resistor.

I have to say that I solved the problem via adding 33pF in parallel to R6 and R14. No oscillation anymore but I have a weird offset of 0.5 V !

Hello Catalin,

    You are correct in needing to increase the noise gain to stabilize the amplifier. Adding capacitor to the feedback is one way, another way is to add a differential resistor. I have attached below the stability Tina-TI file of your schematic which simulates loop gain and the phase margin is very low (-2 degrees). Adding the feedback cap or differential resistor increases phase margin. Try adding a 100 ohm differential resistor instead as shown in the second Tina-TI file (placed snippet of the schematic below the file).  

THS4631_Stability.TSC

THS4631_Attenuator.tsc

Thank you,

Sima

Incidentally, the 2005 model is better, but still kind of low at 18deg. 

Your R across the inputs of course works to increase the broadband noise gain and hence phase margin. The way I prefer to do that is with capacitive noise gain shaping, this is with a feedback cap (which by itself takes the NG to 1, not good enough by itself) than a cap on the inverting node to ground, here is an example LG with those, 

Pretty effective, would need to check the closed loop as well, but if you have a board oscillating you might try 10pF across the feedback with 22pF to ground on the inverting node - all short leads of course, 77deg phase margin now with 2005 model, 

This is just another (of many) applications for this simple concept republished here, 

www.edn.com/.../

Buna ziua Catalin,

Sima is right. There's no phase margin at all in your original circuit and this is the cause of instability and finally oscillation.

I would add two 6p8 caps restoring the phase margin to 54° again.

catalin_THS4631.TSC

Referring to your desired common mode rejection of 100dB, don't forget the impact of manufacturing tolerances of resistors on common mode rejection. Here the worst case with +/-0.1% toleranced resistors:

catalin_THS4631_1.TSC

Kai

And here is that compensated file with the 2005 model, should be ok with the 2020 model also, 

THS4631_Stability 2005 model with comp.TSC

And here is that compensated LG with the 2020 model update, still 50deg phase margin. 

The advantage should be much lower integrated noise using the two caps instead of 100ohm across the input pins. 

And then using Sima's closed loop file, here is the response shape comparison, 

And then here is the output integrated noise comparison, if the output were bandlimited after this stage to say 10MHz, quite a large improvement using the two C's, 

Often a quick way to see low phase margin is to look at output spot noise at the output pin, the original ckt indeed shows that high spike indicative of low phase margin, the inverting C comp with the two caps definitely seems to fix that, 

I am using the PSpice model and I am getting 18º phase margin with no compensation, same as the 2005 model.

That is using the C6=2.2pF at the VF1 node. What is the purpose of C6 ? Without it, phase margin is around 70º with no compensation. That is why I saw no oscillation in simulation and proceeded to implement it without any compensation.

I like the NG shaping concept to add phase margin. Thanks !

Why are you adding C4=C5=C6=3.9 pF when you are breaking the loop ?

Regarding CMRR, I was referring to the OP Amp's CMRR. I am using 0.1% tolerance resistors around the diff. amp since has the most impact on CMRR as you pointed out.

Regarding the output noise at the output pin, my SPICE simulation using the PSpice model (2005 model I guess) shows lower noise when using 10pF across feedback R1 and R6 resistors (resistor designators from your simulation).