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OPA2333: Adder using op-amp

Part Number: OPA2333
Other Parts Discussed in Thread: REF5030, LM7705

Hi Team,

In the circuit below, it is a non-inverting adder configuration of the op-amp. The R148 and R151 form a voltage divider to my input signal +/-5V sine signal to bring it to a level of +/-1.5V sine signal. A 1.5V is added to the +/-1.5V at the noninverting terminal op-amp. The second op-amp is used as a buffer for the reference voltage of 1.5V.
Is there any issue with the setup?.
My doubt is will the 1.5V reference voltage affect my incoming signal.
My input signal +/-5V will be directly fed to an ADC and at the same time, I'm reading this signal through a controller. This voltage divider and adder setup are set to bring the incoming signal down to the input range of my controller.


  • Hi Kai,
    Hope you can solve this problem too.
    I made a buffer at the reference voltage like you said and is working fine.
    Now will this biasing voltage affect my input signal

  • Hi Shibin,

    Here is what I did to resolve your issues:

    1. The op amp circuit is powered with 3.3Vdc in a single supply rail, and you have addition gain of (1 + 15k/10k) or 2.5V/V at last op amp summing stage. So I changed to the unity gain. .In other words, the gains are too high. 

    2. The circuit's DC bias is configured at 3.3(10/22)=1.5V. If your sine input is +/-5Vdc, you need to configure the dc bias at the mid point of 3.3V or higher. I configured the simulation at 1.78Vdc. You may configure it higher depending on your ADC input voltage range.  

    3. The circuit +/-5V generator is using voltage divider to lower the input voltage swing. There are some impedance interference with 10kΩ input resistor, seen in green circle. It will be the best to have another op amp buffer after the +/-5V sine wave voltage divider. I compensated R7 to approx. 5.05kΩ as simulated, which it may work (calculate it from the thevenin resistor and voltage at the input of summing point at pin3, marked in green circle).  Otherwise, there is small dc bias issue at the output of summing amplifier (it may or may not make a difference depending on your application). 

    OPA2333 Adder-1 06152021.TSC

    Enclosed is the above simulation. 

    If you have additional questions, please let me know. 

    Best,

    Raymond

  • Hi Raymond,
    thank you for your detailed answer.
    My intended gain of the summing amplifier is {1+(10/15)}=1.66V/V.
    My input signal to the summing amplifier (after voltage divider) is +/-2V. So why 1.78 biasing is required.
    How to choose the correct bias voltage in a summing configuration?.
    How can we know the impedance interface associated with that particular resistor?.
    Also, every time  I try to simulate in Tina TI, I am getting an error

    How to solve this issue.

  • Raymond's simu works for me:

    Kai

  • Hi Kai, 
    Can you please answer my questions?.

  • Raymond is already assisting Relaxed

    Kai

  • Hi Shibin,

    Q: My intended gain of the summing amplifier is {1+(10/15)}=1.66V/V.
    My input signal to the summing amplifier (after voltage divider) is +/-2V. So why 1.78 biasing is required.

    I was not sure what the requirements are when I simulated the circuit. I was trying to make sure that signals were not clipping in the simulation. I changed to 1.78V biasing per my simulation to provide a little margin for the minimum Vcm required in OPA2333 specification. 

    I need to know what's your output swing range (output mid point and swing from low to high range per your requirements). Currently, the output's mid point is 1.54V with your gain of 1.66V/V.  

    Once I have the output requirements, I will explain the rest of the circuit for you. 

    OPA2333 Adder 06162021.TSC

    Also, every time  I try to simulate in Tina TI, I am getting an error:

    This is likely your computer issue. My guess is that the *.tmp file is not accessible somehow. 

    Best,

    Raymond

  • Hi Raymond,
    Thank you for your reply.
    I'll explain my requirements once again.
    My input signal is a +-5V sine signal. This signal is fed to an ADC.
    This same signal is fed to a voltage divider. The signal thus obtained is fed to an adder configuration with a bias voltage of 1.5V.
    Why I'm doing this is because I want to measure the same incoming signal with my controller also. The input range of my controller is 0-3V.
    What all I've done is to make my +/-5V input signal to a range of 0-3V.
    Also, I am using REF5030 as the reference voltage to the controller. Will it affect the performance of the REF5030 when I am using a voltage divider to generate a 1.5V from this 3V reference IC rather than from a 3.3V source?.

  • Hi Shibin,

    you would enormally ease our conversation when showing a full and complete schematic Relaxed

    Kai

  • Hi Kai,

    Here is my adder

    Here is my reference voltage IC

  • Hi Shibin, 

    Q: What all I've done is to make my +/-5V input signal to a range of 0-3V.

    Here is a way to modify this circuit. You want the output swings from 0-3V and mid point is 1.5Vdc (this is the information that I am looking for)., but there are other solution to the circuit as well.

    OPA2333 has the Vcm shown in the range below. If you use single supply voltage rail, you do not have an operating margin to swing all the way to ground (for the entire operating temperature range). That is why I added -0.233Vdc, which is LM7705 part on the Vee rail. You can do what you prefer. 

    To solve this problem, you may use superposition method. 

    1. Shorted out Vg generator and Vin+ is measured at 0.75Vdc (the voltage divider, I matched the 10kΩ on the lower side of Vg branch). 

    2. Shorted out V1 or 3.3V, Vin+ input is measured at 0Vdc. 

    3. Add step 1 and 2 above and Gain = 2V/V, the output of UA is sitting at 1.5Vdc in DC. 

    4. Since the output needs to swing 1.5V above and below the DC operating voltage in step 3. Vg needs to swing +/-1.5V after the voltage divider (5*6.43k/(6.43k+15k) = 1.5Vp). 

    5. If you have a buffer after step 4, then you can use 10kΩ at R7. As is, R7 is calculated by 10k - 6.43k||15k = 5.5kΩ (you may change to the common resistor values).

    6. After the above calculation is done, the circuit should meet your requirements. 

    If you have additional questions, please let me know. 

    OPA2333 Adder 06172021.TSC

    Best,

    Raymond