OPA192: Question about the offset voltage

Part Number: OPA192

Hi,

Let me know the following,

I think that the offset voltage specs over 0℃to85℃ and -40℃to125℃ in the OPA192 D/S include the effect of Input offset voltage drift.

but when I calculate the max offset voltage @ +125℃ from the max offset voltage@ +25℃ (25uV) and the max offset voltage drift over -40to+125℃ PW package(＋0.8uV/℃),

the result is 25uV+0.8uV/℃＊(125℃‐25℃）＝105uV, exceeds the max offset voltage over-40℃to125℃ in the OPA192 D/S (75uV).

I wonder what to make of these differences?

Thanks

over 3 years ago

+1 Clemens Ladisch over 3 years ago

Guru 267430 points

TI guarantees the 75 µV limit. The worst-case offset voltage and the worst-case drift will not happen at the same time (such a chip would be rejected during testing).

+1 Thomas Kuehl over 3 years ago

TI__Guru* 93105 points

Hello Go,

Clemen's assessment of the OPA192 maximum input voltage offset is correct. They VOS, Input offset voltage maximum's are assured by the datasheet Table 6.7, Electrical Characteristics.

Regards, Thomas

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OPA192: Question about the offset voltage