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TLV3604: LVDS output

May
Genius 9880 points
Part Number: TLV3604
Other Parts Discussed in Thread: TLV3605

Hi,

Customer have following confirmation regarding LVDS output., details below.

"
With TLV3604, if use 5V supply for VCCI/VCCO, what is LVDS output voltage level?
With TLV3605, if use 3V3 supply for VCCO, what is LVDS output voltage level?

Can these LVDS outputs be connected to 1V8 tolerance FPGA IOs?

Wondering whether IC has internal regulator, which converts supplied VCCO voltage to lower voltage level (compliant with 1V8 FPGA). Usually that's the level with FPGAs
"

Regards,
Maynard

  • 0
    Guru 281490 points

    The typical output common-mode voltage is specified as 1.2 V.

    You can connect the output to the FPGA only if two FPGA input pins can be configured as an LVDS input.

  • 0 in reply to Clemens Ladisch
    TI__Genius 11701 points

    Thank you for your support as usual, Clemens. 

    Maynard, just adding on, the output level for TLV3604/TLV3605 is standard with the common mode voltage of 1.2 V and differential voltage swing of +/- 350 mV, regardless of supply. So you should be fine if the FPGA has LVDS ports. 

  • 0
    TI__Guru 53816 points

    Hello Maynard,

    Remember that LVDS outputs are a switched-current *between* the outputs, and require the 100ohm resistor between the outputs to generate the correct logic levels.

    The output follows the LVDS spec, regardless of the supply voltage. So if you looked at each end of the 100 ohm resistor, you would see a voltage swinging between 1V and 1.4V (centered on 1.2V). LVDS is differential and is not designed to be ground referenced.

    Both 1V and 1.4V are in the "high" zone for 1.8V logic, so, as Clemens said, your FPGA needs LVDS compatible logic levels.