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LM8272: LM8272 strange Vout issue

Roy Chou1
Genius 12595 points
Part Number: LM8272

Hi team,

Echo to https://e2e.ti.com/support/amplifiers-group/amplifiers/f/amplifiers-forum/1033559/lm8272-structure-check/3823077#3823077

We follow your suggestion and still see the same issue. (pin5 connect to pin1)

In addition, we also do some measurement to verify the OP state. The result shows that even though we remove OP load and use external power supply. The issue still occurred. Can you let me know whether is related to OP internal design?

- First, we float the OP pin1 and pin2, but ramp up curve still occurred.

-Second, we float pin1/2/3 and use external power supply, the issue still occurred.

In addition, we found that we will see the 178MHz oscillation before OP ramp up. Does it affect the stability of OP?

Regards,

Roy

  • 0
    TI__Mastermind 22381 points

    Hey Roy,

    When you say float pins 1/2 do you mean that you are disconnecting the feedback connection or the load? Also can you clarify what Q17000 gate, stage 2 drain and VD2 are in relation to the circuit?

    This seems to just be a voltage buffer configuration so without knowing what these signals are and how they are relevant to this application I don't know how they affect the circuit.

    Best,
    Jerry

  • 0 in reply to Jerry Madalvanos
    TI__Genius 12595 points

    Hi Jerry,

    Please see my comments below

    Jerry Madalvanos said:
    When you say float pins 1/2 do you mean that you are disconnecting the feedback connection or the load?

    We means that we removed load. In circuit, the OP output will be bias voltage for PA gate. In experiment, we disconnected the LM8272 and PA gate.

    Jerry Madalvanos said:
    Also can you clarify what Q17000 gate, stage 2 drain and VD2 are in relation to the circuit?

    Our circuit is five order PA cascaded circuit.  Q17000 and 2nd stage voltage stand for 2nd and 3rd PA VDD voltage. Currently, we guess that it will generate specific fixed frequency when VD switch and affect the OP leading ramp up issue.

    Roy

  • 0 in reply to Roy Chou1
    TI__Mastermind 22381 points

    Roy,

    This is happening with no load and with an external supply, right? This could be the internal biasing structures turning on. Is this causing an issue in the design? The timing is very short (~6usec). Our devices come out of shutdown (which is a power-on mode) sometimes in 50usec, let alone from a power-off state.

    Best,
    Jerry

  • 0 in reply to Jerry Madalvanos
    TI__Genius 12595 points

    Hi Jerry,

    We saw this issue on existing design, so we tried to remove the load and apply external power supply, but the problem still exist, so we think this behavior is not related to OP load.

     

    This did cause an issue in our design, PA will overdrive when Vg bias ramp up. I don’t think this could be a OP shutdown because OP bias always power on.

    Roy

  • 0 in reply to Roy Chou1
    TI__Mastermind 22381 points

    Hey Roy,

    I was unclear in my previous response. I was not saying the op amp was shutting down, this looks like a power on glitch.

    Here are a couple suggestions:

    1. Ensure decoupling caps are placed close to the device
    2. Test with different loads (100k, 10k) etc and see if it improves
    3. Try slowing the power on ramp
    4. Consider using a device with power on reset (POR) like the TLV9062S

    Best,
    Jerry