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PGA308: One-Wire Interface Timing Considerations

user6356280
Intellectual 315 points
Part Number: PGA308

Section 4.6 of the User's Guide describes the required specifications for the One-Wire interface.

I have a question about the following

・The rise time and fall time are specified as 0.5% Baud, but from where to where is the time specified?　Is it the time between the One-Wire logic level (0.8~2.0V)?

Best Regards,

  • 0
    TI__Guru 51826 points

    Hello,

    As you have mentioned, the PGA308 User Guide/datasheet does not provide a specific threshold for the low to high rise time and fall time. However, a standard UART rise time/fall time specification often used across various UART compatible devices is from 0.8V to 2.0V. This is also in agreement with the logic levels specified for the PGA308. The level 1W interface needs to reach the logic low and logic high thresholds; so using 0.8V to 2.0V on your rise time and fall time timing measurements is correct.  

    Thank you and Regards,

    Luis

  • 0 in reply to Luis Chioye
    Intellectual 315 points

    Thank you for your answer.

    We found that the voltage level regulations for rise and fall times are 0.8~2.0V.

    Also, the datasheet states that the hysteresis is 100mV, what are the specifications for this?

    For example, in the case of a rise from Low to High, the logic goes High when the voltage exceeds 2.0V, but even if the voltage level fluctuates due to noise, etc., does that mean that the logic remains High even if it drops to 1.9V?

    Best Regards,

  • 0 in reply to user6356280
    TI__Guru 51826 points

    HI User,

    A 100 mV hysteresis means that noise levels less than 100 mV won't influence the threshold passing. Which threshold applies depends on whether you go from low to high (then it's the VIH or higher threshold) or from high to low (then it's VIL or the lower one).  Essentially the hysteresis provides some amount of immunity to noise. For example, On a rising edge of the digital signal on the input, the device detects a transition from a logic low to a logic high at the specified VIH threshold.  For example, if the device has detected the transition from low to high, after the digital signal crossed the VIH level of 2.0V and then the digital signal fluctuates 40mV below to 1.960V due to noise, the logic level will remain high since it is within the hysteresis window.  

    Thank you and Regards,

    Luis    

  • 0 in reply to Luis Chioye
    Intellectual 315 points

    Thank you for your answer.

    Your answer was enough for me to understand.

    Thank you for your support.