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OPA835: Error in spice model

Part Number: OPA835
Other Parts Discussed in Thread: OPA2834, TLV9052, , TINA-TI


We are working on a circuit where we are evaluating several operational amplifiers, both from TI and other vendors. The devices we have been looking at include the TLV9052, OPA2834 and OPA835.

We are using SPICE simulations to assess the performance before building prototypes. For various reasons, LTspice is the simulator of choice. This has been working well with TI parts in the past, since the SPICE models can be downloaded from We have been successfully able to simulate the TLV9052 and the OPA2834 in LTspice.

For the OPA835, however, the simulation crashes, and our suspicion is that there is an error in the SPICE model published on More specifically, the simulator are reporting that net 102 inside subcircuit XI21 (CMRR model) and nets 102 and 302 inside subcircuit XI19 (PSRR model) are left floating. By inspecting the SPICE netlist, this seems to be an actual error, as these nets are solely connected to the output of a voltage-controlled current source and a capacitor. For some reason though, PSpice seems to be ignoring this error.

Can someone help me understand how to correct this error? I do believe I will have to modify the OPA835 SPICE model in some way.

To visualize the error, I have made this schematic showing what the OPA835 PSRR model looks like. LTspice complains that nets 102 and 302 are floating.

  • Hello Helge,

      Thank you for providing detailed description and visualization. This error is due to the simulation using infinite resistance for the capacitors CA and CC. The simulation does not like this because it does not see a DC path to ground at these nodes, so it labels it as a floating node. Usually, analysis/simulation profiles there is a setting option where you can change internal resistance of the capacitors or set shunt conductance from 0 to 1p or 1n. This parameter describes the minimum default value of conductance (e.g. the DC path mentioned above) that TINA will allow between any node and ground.

      Other ways to fix this error is by including a very large resistance of 1MOhm or 1GOhm to ground at these error nodes. Howard Bandell has kindly shared the fix to these type of errors for a difference device at this thread. Copied and pasted below for reference, and the bolded are the lines that were added. 

    R1000 NET55 0 10MEG
    *GE0 0 NET67 NET22 NET50 200

    GRA  101 102 VALUE = { V(101,102)/1e6 }
    CA  102 GNDF 1e3
    EB  1 1a VALUE = {V(102,GNDF)}
    R2000 102 0 10MEG


    ED  3 3a VALUE = {V(302,GNDF)}
    R3000 302 0 10MEG

    E1  VO VI VALUE = {V(1a,GNDF) + V(3a,GNDF)}

    EA  101 GNDF 1 GNDF 1
    GRA  101 102 VALUE = {V(101,102)/1e6}
    CA  102 GNDF 1e3
    EB  1 1a VALUE = {V(102,GNDF)}
    R5000 102 0 10MEG

    E1  VI VO 1a GNDF 1

    Thank you,


  • Thank you very much Sima, adding a high value parallel resistance to the capacitors did silence the error message, and the simulation is now running without errors.

    However, now I am facing a new error, in that the opamp is not giving any output signal. I have wired a simple DC-coupled non-inverting amplifier with 6x gain, with a 1 kHz sinewave at 0.2 +/- 0.1 V amplitude. There is no signal at all at the VOUT node, not even 0V or 3.3V, just nothing. Any idea to what might be the problem now?

    (curiously, if I connect the PD pin to ground, the input signal can be seen at the output with a very small amplitude (24.9 mV DC +/- 1.5 uVpp). This is probably the correct behaviour in powered down mode)

  • Hello Helge,

      I am glad it helped with the errors. I tried the circuit on Tina-TI, and it is giving the correct output. 

      That is strange that power down functionality seems to be working, but not normal operation. Would you be able to share your file? I can try looking at it on my end. 

    Thank you,