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# LMH6553: VCLAMP limit

Part Number: LMH6553

In the data sheet, page 4, the maximum VCLAMP voltage is specified as VCM + 2.0V. Note 7 specifies that exceeding the limits could result in excessive device current.

However, the test conditions above the table specify VCM = 0V and VCLAMP = 3V (for the +/-5V condition).

So, should the device be operated with VCLAMP > VCM + 2.0? If so, what is the actual limit?

Best regards,

Eamon Egan

• Note: I realize that the "peak voltage" is specified as 3.0V, but why is it that the normal test conditions for all the other parameters are specified for VCLAMP = 3.0 if this level is not intended for continuous operation?

Since the supply current is specified as max 37mA for VCLAMP = 3.0V, and since this condition should result in excessive supply current, is there a lower supply current when VCLAMP is lower?

• Hello Eamon,

That is a really good point. The electrical characteristics of the LMH6553 with power supplies at +/-5V were tested at this Vclamp peak voltage of 3.0V as verified in the following datasheet figures (page 10 to page 18). While, the electrical characteristics of the device with power supplies at +/-2.5V were tested with Vclamp set to 2.0V for continuous operation.

Usually continuous operation can be defined in hours/days. The amplifier will increasingly ramp up in supply current after a period of time rather than instantaneously at the peak condition. I would recommend looking at Vs = +/-2.5V electrical characteristics on page 5-7 for continuous operation of the LMH6553.

Thank you,
Sima

• Hello Sima and thanks for your reply.

I'm not sure I understand what you mean.

First, you say that the supply current will ramp up slowly - what mechanism in the chip would result in any such long time constant? I can only imagine the mechanism is thermal?

Second, you say that you recommend looking at the +/- 2.5V characteristics for continuous operation. If I want to know how it operates at +/-5V, why would I look at the +/- 2.5V conditions? Or are you saying that the chip is not designed to be continuously operated at +/- 5V ? If so, should not the data sheet make this clear?

Best regards,
Eamon

• Hello Eamon,

Sorry for the delay in response, I am awaiting more details from design engineers on the first question. The mechanism would be due to overdriving the transistors. For the second question, the device is designed for both operations (peak and continuous) at +/-5V.

Thank you,
Sima

• Hello Eamon,

Sorry for the very late confirmation on this issue. They confirmed that overdriving the clamping mechanism does saturate the transistors between common mode and power supplies which increases the device’s quiescent current over time. The parameters in the datasheet at peak clamping voltage are characterized before this increase occurs.

Thank you,
Sima