THS4522: Max sample speed with THS452X / ADC344X

Hello Tom,

  You most likely will need to switch over to higher bandwidth device such as the THS4541 to successfully settle the ADC sampling capacitor voltage below the half LSB of error. The procedure we follow is explained in section 8: Successive-approximation-register (SAR analog-to-digital converter (ADC) input driver design (8), starting with this video. 

   Would you be able to share the schematic and/or simulation circuit of your current design?

Thank you,

Sima 

Well Tom, The ADC3444 is a quad pipeline, not a SAR. But as Sima says - 

1. probably will need a faster part 

2. Looking back, the THS4522 was upgraded by the THS4552 (much better noise and DC prec)

3. If you do need a faster FDA, those normally do not have duals as they start to have crosstalk limitations. 

4. Detailed interface guidance not possible without ckt detail

5. The FDA design is usually including your interstage filter from the FDA to the ADC

6. You normally need either an RC or RLC filter to limit the broadband noise

7. The signal bandwith up to the FDA outputs is quite wide to get fast settling and/or low HD. Can usually be backed off in the filter to improve SNR

8. I usually combine those designs where the overall is 3rd order for a simple RC interstage with a 2nd order MFB in the FDA

Dear,

Please find attached the TINA file of our design.  We have a large number of signals to digitise, so we also make use of multiplexer TMUX1109.  In the TINA file TMUX1119 is used as I didn't find a TINA model for TMUX1109.

The analog signals have a -3dB bandwidth of about 250kHz.

As you can see the values of the charge bucket circuit are those mentioned in the datasheet of the ADC.

Thanks for mentioning the Precision labs videos. very interesting.  Unfortunately I'm not able to find the values of Rsh, tacq and the sample-and-hold capacitor in the datasheet.

I would like to optimise the values of charge bucket circuit of the curent design (250kHz bandwidth / 25MHz sampling) as well as the new design (800kHz bandwidth / 100MHz sampling).  But don't know how to start, missing the values I need to get started with the Analog_Engineer_Calc tool.

Best regards,

FDA_MUX_ADC.TSC

Well Tom, with your relatively low signal bandwidth that you are obviously oversampling, you could probably get by the the THS4552. On your current circuit (thanks for the TINA file), without drilling down too deep yet, 

1. What is your real source impedance, as drawn, the extra R to ground changes the input load, but does not get into the gain balance if the source R is zero - is it? if it is not, you are kind of unbalanced right now - not sure that R to ground at the input is needed? 

2. Are you really running +/-2.5V supply? the ADC probably needs about 0.95Vcm input - kind of running up toward the high end of the CM loop range if set up correctly for the FDA's. You could physically run a single 3.3V solution if you want the and FDA will level shift the Output CM to the ADC requirement if the source can sink the level shift current. 

3. Lots going on from the FDA to the ADC inputs, I am guessing the MUx's are not transparent impedance wise. 

Hi Michael,

To simplify the schematic I put the signal source at the non-inverting input of the FDA.  This input in our design is actually proceeded by a TIA and a second stage amplifier (OPA2381).  At the inverting input we apply an offset voltage to correct for the DC level created by the Ibias and Vos of the previous stages.  Our analog signals are quite low in bandwidth, but we need to take into account that the MUX changes the input signal of the ADC every 200ns.  

If I look at the scope signals of the ADC input, changing the values of the charge bucket circuits does not seem to have any effect...

Best regards,

Hello Tom and Michael,

  Thanks Tom for the Tina-TI file, and thanks Michael for the correction on the ADC type. 

  I would look at these reference designs and app notes on multiplexing at the inputs of the ADC: 

1. Amplifier/Mux/ADC setup example
2. Mux equivalent circuit input to ADC
3. Analog Engineer's Circuit Reference: FDA/MUX/ADC 

  Applications including multiplexing is most popular with SAR ADCs. Pipelines are multiple SH (sample/hold) components in a "pipeline" which has the advantage of increased bandwidth at the price of lower resolution and delays/latency. Please do correct the following statement if incorrect, but from the looks of this application wouldn't you be able to move over to a higher resolution ADC rather than oversampling to gain the extra precision for a switching frequency of 2.5MHz?

Thank you,

Sima 

Hello Sima, Michael

We have close to 100 signals to sample.  Therefore we chose to use multiplexers so we can reduce the number of ADCs (input pins to the FPGA).

I still would like to calculate the optimized values of the charge bucket circuit using the Analog_Engineer_Calc tool .  But as mentioned before, I can not find the value of  Rsh, tacq and the sample-and-hold capacitor in the datasheet of ADC3441.  How would I need to proceed?

Best regards,