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LMV822-N: ESD cell trigger with fast power supply slew rate

Part Number: LMV822-N
Other Parts Discussed in Thread: THS3491, BUF802, TLV9052

Hi team,

I found ex-NSD devices can latch up if power supply slew rate is >1V/us because it triggers ESD protection cell from the thread below.

Do we have any app note or slide about this?
My customer is seeing the continuous 200mV latch after powering LMV822 with ~10V/us slew rate.
Also, they would like to identify which ex-NSD devices have this concern exactly.
Do any op-amps from NSD will have this risk?


  • Hi Kazuki,

    I remember that the BUF802 and the THS3491 have such a slew rate limit in the "absolute maximum ratings". The BUF802 even a limit 0.1V/µs.

    Ultra fast rise time of supply voltage is never a good idea, because it means drastical spike currents running into the circuit and the stimulation of lots of parasitic impedances with the risk of generating dangerous overvoltages and undervoltages at certain pins of OPAmp. Even normal OPAmps without having such an ESD cell which can be triggered by too high supply voltage slew rates have been seen to become damaged by this torture.

    It's more than good design practise that the supply voltage of any OPAmp must be stable, clean and noise-free. An ultra fast slew rate of supply voltage is a clear violation of this rule and must be avoided.

    Even without any supply voltage filtering, the slew rate of supply voltage is limited in the most case by the voltage regulator itself. Assume a decoupling capacitance of 10µF at the output of a 500mA voltage regulator. Further assume that the short circuit current is limited to about 1A, then the slew rate of supply voltage is limited to:

    dU / dt = I / C = 1A / 10µF = 0.1V/µs

    If no voltage regulator with internal current limitation can be used, a RC low pass filter can be introduced in the supply voltage line. Assume a supply voltage of 10V. Then a RC low pass filter of 10R and 10µF can do the trick. The 10R resistor limits the current to

    I = 10V / 10R = 1A

    and the 10µF filtering cap limits the slew rate to

    dU / dt = I / C = 1A / 10µF = 0.1V/µs


  • Hello Itoh-san,

    Maximum recommended supply rise time is rarely documented in data sheets. If this is listed, it means a problem was discovered during device qualification. Long ago qualification plans didn't include this test. Mostly because even older device didn't have ESD specific structures (on supply or maybe any other pin), so this wasn't a problem. Newer devices are tested, but the results doesn't usually make it into the data sheets unless the result is quite low.

    Have you tried TLV9052 samples (the recommended replacement device)? 

  • Hi Ron-san,

    Do we have app note which explains relationship between rise time and ESD cell latch-up?

    I found SLVAEX7, but I can't find specific description about how the fast slew rate triggers ESD cell.



  • Itoh-san,

    Here is a crude ESD cell simulation. This draws current when input rises fast. C1 represents a real cap of the base to collector capacitance.

    If T1 is a low voltage transistor and shunt current was high (like in some low voltage op amps), then secondary breakdown could keep the transistor on until power is removed or the transistor is destroyed.