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OPA694: circuit design

Part Number: OPA694

Dear all,

I am Andrea Celentano, staff scientist at the "Istituto Nazionale di Fisica Nucleare" (INFN), working in the field of high-energy physics.

We are using the OPA694 to design a fast amplifier for a particle physics detector. In the past, we used this component in other circuits, with very good results.

I have a question concerning a detail of the PCB design, specifically the routing of the different signal traces for the OPA 694.

In the picture below, you find a view of the PCB we are designing. This is a 4-layers circuit.

The gray plane is GND. The traces in RED are on the TOP plane. The 6 pads are those were the OPA694 will be mounted (we use the SOT23-5 six-pins DRB package). The top-left pin is pin #1, output. 

As you see, the GND plane is cut all around the OPA 694. However, we have a trace routed on the TOP layer, just below the OPA694 (for design reasons, there is no way to route this trace on the TOP layer in a different way).

An alternative would be to route this trace in an internal layer, by adding two vias, as I report in the image below, where the green trace is in a middle layer. In this alternative approach, the output signal trace does not run below the OPA694, but there are two vias in addiction.

May I ask you what is the preferred configuration, or if these are basically equivalent?

Thanks,

Andrea

opa694.jpg

  • Hello Andrea,

    Thank you for sharing your board images and information about your design.  I have a couple points to address:

    a) Running the trace under the device will not cause issues in your implementation, as there is no switching occurring in the IC.  Keeping the signal trace on the top layer and avoiding vias is a good decision.  Please proceed with the decision to route the output signal on the top layer.

    b) Could you share PCB images with the GND plane in the background, instead of the foreground of the image?  It would help to see how rest of the traces interact with the device.

    c) If you do not have bypass capacitors on your supply pins (V+ & V-), you will need to add them to each supply pin.  The appropriate method is to run a short trace from the supply pin of the device to a nearby capacitor, then route to the via for the power signal/plane.  

    - Please reference the Board Layout Guidelines section of the datasheet, as well as the user guide for the blank EVM board: https://www.ti.com/tool/DEM-OPA-SOT-1B

    - From the PCB images in the user guide you can view how close the decoupling capacitors are to the device power supply pins.  

    d) You actually do not need to cutout the GND plane underneath the device itself for your implementation; the only GND plane cutout I would advise is underneath your feedback resistor network.  The GND cutout removes your shield against noise and could harm your signal trace routed underneath the IC.

    Best,

    Alec

  • Dear Alec, 

    I thank you for your very clear reply! I report below a figure of the PCB design with the GND (gray) in the background. All red traces are on the TOP layer.

    You can see the feedback resistor pads (R11), as well as the filtering C4 and C14 capacitors. 

    If I understood correctly, you suggest to keep the GND plane below the OPA694, and to cut it under the feedback resistor network, right? However, since the trace connecting the OPA694 output (pin 1) to the OPA 694 negative input (PIN 4) - through the bias resistor R11 - passes behind the OPA, then the GND plane should be cut also there?


    Thanks again!

    Bests,

    Andrea

  • Hello Andrea,

    Thank you for providing the additional clarity.  

    I have a couple questions:

    1) R5 looks like a resistor on the input signal path.  Is the trace going to the left of R5 a connector, an IC, a test-point?  Does this signal stay on the top layer?  Depending on what signal is being provided to the noninverting input of the amplifier, you could move R5 around to different parts of the PCB layout.    

    - If you are comfortable moving R5, it would be better to place your filtering capacitors as close as possible to your supply pins.  Especially for high speed amplifiers, it is important to have these capacitors near to device pins.  I also would avoid routing your power signal from pin to capacitor pad with a via; it is ok to use vias for power signals, but the ability of the capacitor to provide filtering is limited when you connect it to the power pin with a via.  I'll attach a quick sketch on top of your board so you can see what I am describing: 

    This image is just a suggestion of how close/tight of a layout you could implement for better performance results.  You should choose and be comfortable with the right amount of tradeoffs; you know more about your overall design.  As you can see above:

    a) Filtering/bypass/decoupling capacitors are very close to supply pins of the OPA694

    b) Vias to the power or GND plane can either be on the capacitor pads (like in the EVM I mentioned in my previous post), or after you route the trace to the capacitor from the OPA694, as pictured above.  You should also consider using either one regular/normal sized via for power signals, or a group of smaller vias on top of a pour/polygon.  I show only one via for each here, because I did not draw this layout in PCB software.  

    c) Are you routing the long GND trace on the edges of the PCB for EMI/shielding?  If so, that is ok to keep.  However, I recommend routing GND signals coming off the OPA694 to the GND plane directly rather than skinny traces to a test point.  You may want to terminate the gain resistor R10's GND connection into a via, and then decide whether to tie it to the perimeter trace or not.  If you have experienced success using this approach before, I would caution you to keep a lot of vias & pours/polygons to the GND plane, so return currents are not travelling all along the board on skinny traces.  Please see my attached document below for more information.  

    d) The shadowed area under R11 (Rf) depicts where you could perform the GND cutout.  The difference between keeping your existing GND cutout and adding to it, vs filling in GND under the IC and only cutting out under R11, is something I am unsure of for your PCB.  Since the OPA694 can operate at high frequencies in excess of 1000MHz, you could leave in the cutout and follow the approach of the OPA694 EVM, which includes a GND plane cutout under the device as well.  I would add however, that you generally do not want to cutout the GND plane under power signals.  The EVM does not abide by this rule, so I feel you can choose which approach you would like.  Please do cutout GND under R11, traces to OPA694, and under the OPA694 inverting pin & output trace end, at minimum, if you decide to remove your existing cutout.  

    In general, in high speed analog layout, long skinny signal traces can create more inductance and capacitance for you design.  If you are curious about high speed layout and want to implement some more best practices in your design, I am attaching a TI resource for this.  I also understand if PCB layout is not a core part of your research or responsibilities; I am happy to help and answer questions either way.  

    slyp173.pdf

    Hopefully this all makes some sense and helps your design!

    Best,

    Alec

  • Dear Alec,

    thanks for your very clear and detailed answer! The GND trace on the edged of the PCB are for EMI/shielding, as you say. In the past, in a similar design, we exploited a similar solution, obtaining a very good result. I thank you for the suggestion concerning the gain resistor R10 GND connection, we will connect directly to the GND plane using a via.

    I also thank you for the suggestion regarding the C4/C14 capacitor - now that I look at it more carefully, it is absolutely clear that C14 is not properly placed, and we should modify it so that the polarized pin is directly in contact with the OPA694 negative voltage pin.

    I also thank you for the suggestion concerning the GND cutoff.

    We will now update our design, and move forward toward the production of a first batch of circuits for test and validation.

    Thanks again,

    Andrea

  • CIao Kai,

    thanks! Indeed, very interesting topic, thanks for pointing it to me.

    Bests,

    Andrea