THS6182: I ADJ pin resistor or low negative voltage

Hello Amishav,

I would like to ask a clarifying question before I research an answer for you:

Q: Are you asking if using either of the two methods you proposed are valid uses of the THS6182 in a circuit?

Q: Are you asking how either method would affect performance, stability, etc of the THS6182?

Q: Are you using 1K resistors to limit and/or lower the bias current of the device?

Q: What is your goal for this implementation?

Best,

Alec

To clarify - we have a legacy design in which the IADJ pin is connected as I described. The circuit is used as a high frequency power amplifier. We isuued new modes of operation and experiencing performance issues, mainly: when changing the 2 BIAS pins from 1 to 0 to enable the output. This results in a kind of "overshoot" which takes ~100us to relax, making the new modes useless.

Hello Amishav,

   The IADJ pin should be connected to ground via 0ohm resistor for maximum device bias current. Bias pins, BIAS-2 and BIAS-1, should be used to control the power modes of the device. The transition time between modes is specified to be around 1us. 

Thank you,

Sima 

This doesn't answer my question.

I probably need a TI's CHIP EXPERT's opinion: what will be the impact on the performance of THS6182 if (-)150mV is applied to the IADJ pin, via a 100K resistor?

Hello Amishav,

I am going to connect with our design team to confirm the expected performance for such a circuit configuration.

Best,

Alec

Hello Amishav,

While I am working on understanding exactly what performance impacts your implementation could have on the THS6182, could you share any additional data or information about the overshoot and other tests performed?

Also, is the existing legacy hardware for the THS6132, and being prepared for use with the THS6182?  I noticed the transition time from logic high (1) to logic low (0) is 5x longer on the THS6182 than the THS6132 device.

Best,

Alec

Hi,

1. my bad - THS6132 is not part of this issue, it's I typo and I have edited the post.

2. here is a waveform showing: a. GREEN - Bias1+Bias2 (used as a DISABLE signal). b. VIOLET - the reference signal (pin 8 of QFN - D1IN+). c. ORANGE - THS6182's output; the overshoot is visible very clearly.

Thanks,

Amishav.

Hi Amishav,

counterquestion: Does it work properly when you connect the IADJ pin to ground via 0ohm resistor?

Also, according to footnote (4) in the datasheet, concretely spoken the specified transition times between the modes refer to the period of time the supply current needs to settle to half the final value, but this does not say anything about the setttling time of output signal. Settling time of output signal can vary with the actual circuit. Can you show a schematic? 

Kai

Hello Amishav,

Thank you for sharing the waveform.  I will second Kai's questions; have you verified the circuit works as described in the datasheet with a 0 Ohm resistor path to GND from the IADJ pin?  Could you share a schematic and/or additional design details about the necessary modes of operation?

Best,

Alec

Hi Kai and Alec,

I was hoping to find an explanation and save the 0R modification and testing, but it looks like I cannot escape this step.

I am not sure it's ok to share the design here - IP and so on, so will skip it for now. However the overshoot does not seem to be related to the feedback or the rest of the surrounding circuit.

Thanks,

Hello Amishav,

  It would be helpful to debug if you are able to replace the resistor with a 0 ohm short. If that fixes the issues, then we can pinpoint the explanation. If that does not fix the issue, you may share the design with us offline for further analysis. 

Thank you,
Sima