OPA2863: AC PSpice Simulation for Stability + Monte Carlo

Well Anthony, the answer is neither - you need to break the loop and inject a signal tracing it around the loop. There is quite a lot on that topic, in the FAQ there is this discussion, 

https://e2e.ti.com/support/amplifiers-group/amplifiers/f/amplifiers-forum/1048137/faq-documents-about-op-amp-stability

Hi Michael

Many thanks for the link, will help a lot !

Do you have an answer regarding my second question ?

Regards,

Anthony

Hello Anthony,

  An engineer on the team is currently working on an outline covering temperature-dependent components in a 'worst-case' scenario to evaluate the extremes of the device's temperature range. Please see this thread: https://e2e.ti.com/support/amplifiers-group/amplifiers/f/amplifiers-forum/1094455/lmh5401-sp-se-to-diff-front-end-for-adc12d1620qml-sp---monte-carlo. 

Thank you,

Sima 

Hi Anthony,

showing a phase margin of 31° your circuit doesn't seem to be very stable, unfortunately:

anthony_opa2863.TSC

Kai

Hi Kai, thanks for your answer.

I've tried to follow the analysis method described on TI precision Lab (https://training.ti.com/ti-precision-labs-op-amps-stability-spice-simulation?context=1139747-1139745-14685-1138805-13850)

Hereafter the simulated schematic:  (simplified compared to the previous one, input impedance adaptation removed, schottky diodes removed)

Hereafter the AC analysis curves:

with:

Aol = Vout/Vfb

Beta1 = 1/Beta = 1/Vfb

Vout = AolBeta

Two questions:

1- On your simulated schematic, you open the loop in a different way compared to what is described on TI precision lab, why ?

2- My results are complety differents than yours ? Why ?

Thanks for your support

Regards,

Anthony

Hi

Thanks for your answer and sharing, I will try to follow your method asap and come back to you

Regards

Anthony

Hi Kai,

Many thnaks for your quick support

Ok for your method, I will have a look on it (If you can provide me the link to Michael Steffes article)

We have the same results for the sencon simulation, but impossible to reproduce the Bode plot (with 31° margin) you provide for the first schematic. I tried to plot it (only schotty diode are removed):

Do you understand why my result is so differents than your ?

Regards,

Anthony

Hi Anthony,

the link is here:

https://www.planetanalog.com/stability-issues-for-high-speed-amplifiers-introductory-background-and-improved-analysis-insight-5/

Anthony Boulard said:

We have the same results for the sencon simulation, but impossible to reproduce the Bode plot (with 31° margin) you provide for the first schematic. I tried to plot it (only schotty diode are removed):

The junction capacitance of the Schottky diodes is part of the problem because they degrade the phase margin.

But the major cause of difference is that you have unwantedly (?) moved R1 (R10 in my simulation) into the feedback loop:

Kai

Hi Kai,

Thanks for the link

Yes you are right, R10 was in the feedback loop... I perform an AC analysis with R1 out of the feedback loop, pretty same results :/

Can't find fc = 400KHz as you shown on your 1st measurement...

Regards,

Anthony

Hi Kai,

Sorry you're right

So on my last simulation, I find 20° phase margin (Fc = 9,4Meg). I'm still very far from your 1st result (31°, Fc = 24Meg)

Why a such difference ?

Thansk for your support

Regards,

Anthony

Hello Anthony,

Are you trying to replicate Kai's results using the method taught in TI Precision Labs?  I am curious how you justified removing certain aspects of Kai's design when attempting to replicate Kai's simulation.  Have you tried running Kai's simulation as is?  I retested Kai's file today (in the configuration that was posted, no modifications) and was able to achieve the same results.  I am using the TINA-TI simulator w/ the 2021 REV D model of the OPA2863.

You are unlikely to find the exact results as Kai if your circuit differs greatly; SPICE simulators take a lot of factors into consideration and removing a diode or several capacitors may affect convergence or the stability of the circuit.

Between these two options, what is your current priority?

1. Aligning your circuit with Kai's initially posted results, which is still unstable but better than 20 degrees PM?

2. Stabilizing your circuit (or a close variant) to a PM greater than or equal to 45 degrees?  

Were you able to implement any worst case simulations?  I just want to clarify what we are accomplishing now with this thread .

Best,

Alec

Hello Alec

Yes, 1st step, I'm trying to converge with Kai first results, both methods should converge even is they are differents. I'm just surprise that removing clamping diodes affect the stability of my design. I just want to be sure that TI precision lab method can be applied to my design (and futur designs also)

Sure, 2nd step I'd like to stabilize my design an increase le PM

3nd step, perform worst case analysis

But you're righ, let's move to the 2nd step

Hope it's clear

Thanks for your support

Regards,

Anthony

Hi Anthony,

there's again a mistake in your schematic: "vout" must sit directly at the output of OPAmp, not at the capacitive load.

Kai

Hi Kai,

Ok, I was wondering where I need to place VOUT. Now we are aligned on results

So 32° phase margin and a rate of closure Aol - 1/Beta (1/Beta is Beta1 on the plot) of 32dB/Dec (between 1Meg and 10Meg), so pretty unstable, has you mentionned on your 1st answer