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AMC1300: TINA Spice simulation with common mode voltage step

Part Number: AMC1300
Other Parts Discussed in Thread: AMC3301, AMC1350, AMC3330, AMC1311

Hi,

I modified the TINA simulation of the AMC1300 for voltage measurement. We wanted to see if the spice model shows any change in performance with splitting the main resistor divider and putting the common mode voltage step with respect to the bottom of the resistor divider instead of between GND1 and GND2. We modified this spice model (https://www.ti.com/lit/tsc/sbam448), changed the dc voltage source to a step voltage source for a transient simulation. The modified simulation shows dc current flowing across the isolation barrier, so we apparently can't use this model to simulate a CM step with a split divider? Is there any way to fix this?

sbam448_modified.TSC

  • Hi Andrew,

    The current that you see flowing across the barrier is caused by TINA requiring all nodes to be referenced to TINA GND. In this case, the GND1 net's TINA GND reference must flow through the bottom leg of the resistor divider and the Ampere meter. 

    When sensing a voltage in a split divider fashion, using R3' is not necessary as a split-tap connection can be used. This involves replacing the sensing resistor R3 with two sensing resistors of half the original value and connecting the high side ground, GND1, between them. Thus, the bias current flows evenly from both inputs to ground and there is no undesired offset voltage. Please see the simulation I've attached for an example and please let me know if you have additional questions. 

    1323.VLL_sense_AMC3301_AS.TSC

  • Interesting. Does this method you've shown have any difference in the common mode rejection ratio? I see that it does also change the common mode at the input pins from half the differential input value to zero. And if the bias current flows evenly, then as you said it eliminates any offset error caused by the bias currents, which is nice to eliminate the problem that R3' solves.

    I did see that it allows me to simulate in TINA a CM step from GND2 to the bottom of the resistor chain. Though the fact that the model can't handle the other case gives me a little pause on trusting the CM performance of the TINA model.

    sbam448_modified_splitResistor.TSC

  • I would expect an improvement in common-mode rejection ratio since the resistor divider circuit is balanced with respect to both inputs when using the split-tap connection. Whereas with the R3' circuit the negative input may see a slightly attenuated signal compared to the positive input in some cases. 

    The "AFE" model for SBAA350 is intended to show proper simulation behavior when balancing the circuit in the R3' configuration to cancel the offset created by the input bias current flowing through the R3 sensing resistor; used in conjunction with SBAA350: https://www.ti.com/lit/an/sbaa350a/sbaa350a.pdf and this excel calculator: https://www.ti.com/lit/zip/sbar013. The "AFE" circuit was not designed for CM performance - I suggest shorting/deleting the "AFE" circuit and re-running the simulation with the split-tap connection.  

  • Alex, Thanks for providing that TINA simulation with the split-tap. We've seen lots of datasheets for the AMC family, and haven't seen this method proposed before. Have I just missed some documentation, or why haven't we seen this proposed before? E.g., even the AMC3301 datasheet and app notes don't show this approach. It makes a lot of sense to do it this way, and it eliminates the bias current induced error that R3' is trying to solve.

    Splitting the high-impedance resistor into two halves should also be similar to having a 1MOhm CM choke. Any capacitance between the input pins and your noise source are behind a few MOhm with the split pin, whereas there is little or no impedance between the input pins and one side of your voltage measurement circuit.

    One of the reasons for this discussion was that we were trying to decide where to put filter capacitors on the R3' implementation, and wanted to see if the SPICE model showed any difference of where the capacitor is placed. We originally just had a small filter cap across IN+ to IN-, but weren't sure if that was balanced in a high frequency sense (vs. two capacitors, IN+ to chip gnd and IN- to chip gnd). 

  • Hi Andrew,

    Happy to help and I appreciate the additional background! It is not always the recommended method for voltage sensing as a higher input impedance device such as AMC1350, AMC1311 (unipolar input) or AMC3330, will have a smaller likelihood of a gain error due to input resistance variation that is in parallel with the sensing resistor. Quantifying this effect can be seen in the voltage sensing excel calculator that I posted in my previous post. However, for customer's that are ok with this potential error contribution or plan on performing a gain calibration it is not a concern. We do plan on releasing a circuit cookbook document showing the split tap method however and plan to have it online before the end of the year. 

    We typically recommend a cutoff frequency of ~1MHz for a differential anti-aliasing filter on the input, 10ohm+10ohm+10nF for low impedance sensing. With a resistor divider, the two additional resistors can be removed and the differential capacitor value can be reduced. For applications with high common-mode noise we recommend adding additional common-mode filter capacitors from the input to ground. The capacitors should be 10x+ smaller than the differential capacitor value and place as close to the input pins as possible. 

  • Just to clarify, for the common-mode capacitors, you mean from INN to GND1 and INP to GND1? Would it cause problems to use the same capacitor for the differential filter capacitors and the common-mode filter capacitors?

  • Correct. The resistance from the resistor divider and differential capacitor between INP and INN should attenuate the majority of high frequency noise. The common-mode capacitors, INP to GND1 and INN to GND1, are recommended to be smaller than the differential capacitor. Best practice would require the common-mode capacitors to be at least 10x smaller than the differential capacitor to limit potential distortion caused by tolerance mismatch. Of course, this depends on the individual needs to of the signal chain and I recommend testing a few different values once you have a system on hand for best performance.