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OPA192: output jitter

Part Number: OPA192

Hi team,

My customer use OPA192 in their project. And they meet below issue, could you please help give some comments? Thank you!

When an avalanche breakdown occurs in the MOS, the voltage at point A will be 520V, while the output at point B will be 4 V, the rise time of the output waveform will be 340ns, and jitter will increase. May I know what causes the output jitter?



  • Hello Ivy,

    I suspect the jitter is actually noise being added to the fast slewing input voltage applied to the amplifier circuit. The circuit has a number of high resistance resistors that will directly generate significant thermal voltage noise, or generate voltage noise converted from the op amp's input current noise flowing through the resistances. Of particular interest are the two 500 kilohm series input resistors through which the OPA192 input op amps input currents flow. Each side of the circuit contributes noise in root-sum-square manner. 

    I suggest an experiment. Scale the 500 kilohm input resistors down to 50 kilohms, the 4 kilohm resistors down to 400 Ohms, and increase the 100 pF capacitors to 1 nF. Short out the 3.92 kilohm resistors as all they are doing is adding thermal voltage noise to the circuit. Then, test the circuit and see if the jitter decreases. The resistors in the OPA192 output stage could be scaled as well, but try the experiment on the input stages first.

    Regards, Thomas

    Precision Amplifiers Applications Engineering

  • Hi Thomas,

    Thanks for your comments.

    Because it is a project that's already in production, and we replace competitor device in this project.

    So the customer don't like to make too much modification, such as the input and Rf resistor.

    In addition, the customer think increase the capacity will affect the rise rate, they need a fast rate of rise.

    May I know if there is a better choice of devices in the system?

    Besides, from below figure, we can see the bandwidth in G=100 is about 100kHz.

    Customer guesses that bandwidth is too low at this point, which affects system stability.
    Could you please help give some comments?
    Thank you!



  • Hi Ivy,

    please explain what DC potentials are connected to "A-" and "A+". Where exactly is the ramp applied? How is the ADC with its charge bucket filter connected to the last OPA192? Can you show a complete schematic of this section?


  • Hi Ivy,

    Please provide a like image for points A and B with the competitor's op amp in place of the OPA192. And the information Kai has requested is needed for a more meaningful assessment.

    Regards, Thomas

    Precision Amplifiers Applications Engineering