The TI E2E™ design support forums will undergo maintenance from Sept. 28 to Oct. 2. If you need design support during this time, contact your TI representative or open a new support request with our customer support center.

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

INA240: Output offset

Part Number: INA240


I am simulating the INA240A2 with LTSpice (or Tina TI gives the same results) and I have an output offset of 29mV when the input is connected to the GND. This offset is here when I have a current below 80mA in my schematic. I try to understand from where comes this offset. It corresponds to an input offset of 600uV. Can you explain this offset?



  • Hey Mathieu,

    The offset you are measuring is partially due to input offset and mostly due to output stage swing-to-ground limitation. Since you are setting reference voltage to 0V and Vsense is also 0V, the output stage is slamming into ground rail so output is saturated and not linear. The 29mV swing-to-ground (Vsg with Vsense=0V) could be accurate since we do not specify this behavior when there is no load resistor (RL) at the output. We do specify Vsg with RL=10kΩ and this value is 10mV (see datasheet); however, as you increase RL, the Vsg will always get worse (increase) because smaller RL always helps pull down VOUT.

    I would try placing a 10kΩ load resistor to see if behavior changes.

    If you are wondering well what is the minimum, linear Vout value possible when RL=open. This should be 50mV because in the gain error specification we specify Vout going from 50mV to (Vs-200mV) in the testing condition.

    I hope this helps.



  • Hi Peter,

    Thank you for your answer. I tried to simulate with a 10k load on the output but I still have an output voltage of 29mV.
    I am agree with the max swing to GND of 10mV and the input offset voltage of 25uV (it gives 2.5mV on the output ).
    But it remains 17mV to explain.



  • Hi Mathieu,

    what you see is just the simplified output saturation voltage implemented by the INA240 Spice model:

    Compare with figure 7-13 of datasheet.


  • Hey Mathieu,

    The current INA240A2 model shows that its linear output begins at around 45mV, which aligns with the 50mV Vout testing condition for gain error; however, Vout min at 0V Vin is around 29mV and this does not align with the 10mV specification. While we do not guarantee gain error linearity in between 10mV and 50mV, the minimum Vout should be closer to 10mV + Vos_cmrr +Vos_cmrr +Vos_rvrr.

    I just so happen to soon be releasing a model called INA240-SEP, which is essentially the INA240A2 in space enhanced plastic. The datasheet specifications are very similar if not the exact same. I have attached this model here, but will be releasing this model online for INA240-SEP and INA240Ax (in a few weeks) as the models are similar. This model I am attaching uses a slightly different architecture, but the output is linear down to ~1mV, so if you need this behavior of minimum Vout to 10mV, then you could use this model in the mean time. Refer to the model header for complete performance.