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INA200: General Query w.r.t uncertainties

Thomas Funk
Prodigy 20 points
Part Number: INA200

Hi there,

I have an application that runs on less than 1mA, therefore my planned design is as above. Three areas of concern/uncertainties arise and are:

1) To minimize quiescent current, can I set R1 & R2 to the values as shown above? The datasheet states that the maximum Input Bias current is 15nA, therefore 1 Mega-Ohm should not pose any problem as it is still >50 times smaller than the expected input impedance into the INA200's comparator. Am I right in the interpretation of this specification?

2) The Comparator's output is rated at 18 Volt Max, but the datasheet says this can be exceeded provided the current is kept below 5mA. My circuit has effectively 20 kilo-ohm to 40V, resulting in 2mA of current and therefore within the clause, but surely all transistors/FET's have a breakdown Voltage, therefore what is the actual breakdown Voltage and if it is indeed exceeded with the current limit in-place, will the circuit still function correctly or will it be in an undefined/latch-up state?

 3) As for my reset, I like to have an additional 4 second delay (in hardware), hence the 1uF capacitor added to the reset input and relying on the internal 2 Mega-Ohm as my discharge resistor to set a rough time constant (accuracy is not a concern). Can the reset input handle such a slow voltage decay on its input or will it behave unpredictable? i.e. is it a Schmitt trigger type of Input with its low threshold at about 1.1V or is it some other circuit that will go into a "linear" region with potentially "bad" behavior? Section 7.3.3. in the datasheet does not give any detailed rationale behind the RC circuit nor on maximum limit of the capacitor that is allowed to be used in the RC Filter. I will be driving it with 5V and after removing the 5V (Same as on V+ of the INA200), I want an additional 4 second delay (approximate). Mine is not a case of driving it with a different voltage than V+ for which section 7.3.3 seems to try and address.

Regards

Thomas

  • +1
    TI__Mastermind 30810 points

    Hi Thomas,

    Here are my answers to your questions:

    1. Your interpretation of the comparator input impedance is certainly correct. There will be approximately 15mV additional uncertainty, or part to part variation, on top of the 30mV comparator threshold tolerance (590mV to 620mV at room temperature). Thermal noise is another factor.
    2. You’re correct that according to datasheet it is allowed to exceed absolute max rating while current is limited. The configuration you specified should be OK. The device will not function normally though. The datasheet statement simply means the device will survive without physical harm. In order for it to function as specified, operating condition should be within spec and certainly within absolute max ratings.
    3. The /RESET pin comes with a Schmitt Trigger type conditioning gate. Slow ramp should be OK. With the scheme you proposed, the reset will have a slow falling edge which accomplishes the delay needed. But there may still be a fast rising edge, depending on your driver. The datasheet recommends a 1uS rise time for reliability.

    Here are some additional observations:

    The device quiescent current is about 1.8mA. is it acceptable for your applications? The 100Ohm sense resistor is quite large. Together with the amplifier input bias current (16uA), it may cause a fairly large measurement error.

    Regards, Guang

  • 0 in reply to Guang Zhou
    Prodigy 20 points

    Hi Mr Guang,

    Thank you for your reply. Questions 1) and 2) above are resolved with your answers. In my final solution I won't use 1 Mega-Ohm and the 4.7 Mega-ohm as my current consumption is not that critical and I am aware of the thermal noise theory for high valued resistors. Also compared to the device's quiescent current, it makes no sense to use such high valued resistors. I did exaggerate the values for the question to ensure the comparator's input impedance gets the focus full-on.

    As for question 3), thank you for your input, it did partially answer my question. For interest sake, do you know what the /Reset pin's threshold is for entering the latching state as the threshold in the datasheet seems to be the threshold for entering the reset/transparent state. In other words what is the hysteresis on the 1.1V listed in the datasheet for the /Reset pin input. And does it change with the device's supply Voltage.

    Further the datasheet does not explain nor give any formulas for determining the appropriate RC filter's time constant. It only gives 2 sample values. Neither does the datasheet state whether the required rise time is the minimum or maximum rise time, but I take it as the minimum required rise time else the logic of adding a RC filter doesn't make sense. And I presume only the rise time needs to be slowed down as the text only refers to rise time. Is this indeed the case? Perhaps the datasheet can be improved for its next iteration/release on this point. And what behavior is inconsistent if not heeded?

    Regards

    Thomas

  • +1 in reply to Thomas Funk
    TI__Mastermind 30810 points

    Hi Thomas,

    For question 3) – I would treat the /RESET pin threshold as the boundary between latching and transparent states. Unlike that of the comparator input, hysteresis for this pin is not as important. This is likely the reason why the threshold is specified in the datasheet as a typical value, without min/max. When noise is taken care of by the comparator hysteresis, its output should be stable, the /RESET threshold becomes less critical.

    I agree that we could have done a better job in describing the RC filter in the datasheet. What it really wants to convey is that a rise time greater than 1uS is good. I would go a little further to make it 2uS for more margin.    

    Regards, Guang

  • 0 in reply to Guang Zhou
    Prodigy 20 points

    Thank you Guang for your assistance. I am sure I can continue to finalise my design now based on all the above answers provided.