Other Parts Discussed in Thread: TINA-TI
Hi,
Whilst simulating this for a design I am working on, it has left me scratching my head a little. I have tried to tie the open-drain outputs to the recommend pull-up resistor, we know that when two open-drain outputs are tied together, this forms an AND gate. The output is high only when both switches are off, if either are in different states, then the output is low.
So, the setup is OUT1 and OUT2 are tied together through a 4.7k resistor, however the output is pulled low via OUT2 continuously, when it should be pulled high again when the overvoltage condition is met on OUT1. Connecting them to their own separate resistors works well, as expected however this is not how I wish to see them function.
Looking at the internal functional block diagram of the chip, there is nothing to suggest that this should not work in this mode, is there a fault with the model?
I have tried LTSPICE and TINA-TI and receive the same results in both software.
Any chance any one could shed some light on this for me, maybe there is something obvious I am missing.
Something else that concerns me,
'Both open-drain outputs power up in a high-impedance (Hi-Z) state when the low-side supply (VDD2) turns on. After power-up, if the high-side is not functional yet, both outputs are actively pulled low.'
does this mean that the OUT1 and OUT2 are pulled low, thus anything connected to the output of them will also be pulled low, or does this mean the MOSFETs are pulled low, and thus if there is an external pullup the output should remain pulled high?
H
