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XTR111: EF pin not work when VSP voltage over 19V

Part Number: XTR111
Other Parts Discussed in Thread: PGA900, TVS1401

Hi:

I meet a problem about XTR111 EF pin. When voltage on VSP over 19V, the EF pin not be low when wire disconnected.

The EF pin pull low function well from 7V to 19V (VSP voltage).

Here are schematich, pull high voltage AVDD is 3V. I use PGA900 GPIO1 to detect the EF pin signal.

Would you help to give any sugggestion for the issue?

  • Hi Hao,

    The XTR111 error flag is able to detect the open-circuit, wire break, or high load resistance when the output voltage of the XTR111 approaches the VSP=19V supply.  The XTR111 output compliance voltage extends at least 2V from the supply (at least 17V when VSP=19V).  

    However, in the schematic above, the TVS1401 clamp protection has a VBR breakdown voltage between 17.1V and 17.6V.  Hence, when the XTR111 output voltage starts reaching ~17V, the TVS1401 clamp starts turning on and draws the XTR111 output current, providing a path for the output current.  Therefore, the XTR111 error flag never sees an open-circuit or wire-break condition since current flows through the TVS1401.

    If you remove the TVS1401 clamp, the XTR111 will be able to detect the open circuit condition when VSP=19V.

    If you plan to use the XTR111 with a VSP supply voltage at 19V, then you will need to select an external clamp with a standoff voltage around 19V,  otherwise, the error flag will not  be able to detect the open, since the TVS1401 limits the XTR111 output voltage and provides a path for the output current to flow.

    Thank you and Regards,

    Luis 

  • Hi Luis:

    Thank you very much, the issue has fixed .

  • Hi Hao,

    also keep in mind that C6 and C7 cause a short circuit current to flow into the XTR111 when the /EF output toggles low. Such a short circuit current spike not only has the potential to damage the XTR111 but also causes nasty ground bounce within the XTR111 and ground noise in the whole circuit. I would think about adding a current limiting resistor in series to the /EF output.

    Kai

  • HI Hao,

    Thank you, I will close this post.  Let us know if you have additional questions.

    Thank you and Regards,

    Luis