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Original question:

OPA692: Dc-offset at the output voltage of a buffer circuit

OPA692: Using of OPA656 in a noninverting level shift circuit

Kara
Prodigy 40 points
Part Number: OPA692
Other Parts Discussed in Thread: OPA656, TINA-TI

Thanks for your suggestion in the previous answer. The rise time of my signal is 30 ns and OPA656 looks very good for my application. I also tried to use it for a level shift. I defined the noninverting level shift parameters by using Analog Engineer’s Calculator to shift my voltage from [-2.5V 2.5V] to [0.5V 3V].

When I use the resistance values of Analog Engineer’s Calculator, the bandwidth decrease dramatically. When I decrease the resistance values 10 times, the bandwidth increases almost 11 times. Why does the resistance value of the noninverting port affect the bandwidth significantly?

Secondly, I would like to shift my voltage from [-2.5V 2,5V] to [1V 3.5V]. In this case, the simulation time is very long compared to the previous case. Moreover, the high state of the output voltage is around 3V instead of 3.5V (see below). What could be the reason for this?

Below you can find the Tina-ti file of my simulation circuit.

Best regards,

Kara


level_shift_120.TSC

  • +1
    Guru 48395 points

    Hey Kara, that is kind of an interesting tool. Likely done by the lower speed precision guys who maybe don't care as much about source impedance and noise issues. 

    Couple of fields they should add to the outputs is total source R and resulting Johnson noise. 

    Here that will be, 5kohm source (8.9nV added noise at the V+ input). That 5kohm will combine with the model parasitic inputs C of 2.8pF (for the OPA656 in your file) to give an added pole at 11MHz - far lower than any of the parts you menation gain of 1 BW. Also, for this approach at higher speed, your source needs to be able to sink the level shifting current and the bias voltage source needs to be low impedance through higher F.