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TLV3201-Q1: Phase Inversion Fig 25 Question

Part Number: TLV3201-Q1
Other Parts Discussed in Thread: TLV3201


I have a question about Fig 25 from the TLV3201-Q1 datasheet. It seems the intent is to show that input voltages on either the IN+ or IN- pins of the device that exceed the rails (VCC or GND) will not cause phase inversion in the device output. I'm a bit confused by the plot, the blue line shows the output, which seems to be swinging between +/-2.5V while the input voltage swings between the same values.

Since the part is a single supply part, I'm not sure why the output would be centered around 0V. I'm also not quite sure at what voltage level the Input is actually at, since it's swinging about 0V as well. 

Is the output voltage on a different scale (not shown that is actually 0V to 5.5V)?

What is the input voltage relative to? Is 0V on the input scale suppose to represent VCC so this is showing an input at VCC + 2.5V and VCC - 2.5V?

Thank you!

  • Hello Tyler,

    Yes. It was measured with split ±2.5V supplies. Several of the graphs hint at split supplies.

    Depending on the test, it may be easier to test with split supplies than single (not having to level shift). The production tests on the testers are actually done with split supplies.

    The comparator does not care if it is single or split supplies. It will still refer to the negative pin as it's reference.

    With split supplies, 0V will be mid supply. So 0V on the scale would be equivalent to +2.5V on a single +5V supply.

  • Hi Paul,

    Thanks for the response. Totally fair, I guess I was thinking too narrowly. Ok. With that being the case, on 2.5V split supplies, it seems like the input is swinging to the supplies, is it just a graph resolution issue, and the inputs are actually swinging past the supply voltages?



  • Hi Tyler,

    It's hard to see on the graph that the input signal is exceeding the +2.5V and -2.5V supplies by ±200mV - so, yes, a resolution issue.

  • Got it, totally fair.

    I know there has been discussion on this in some of the other forums, but has there been testing done to the ABS max (VCC + 500mV and 0 - 500mV) to verify no phase inversion? I guess asked a different way, if the current into the device is limited such that the ESD diodes can adequately keep the inputs to within their 400mV breakdown, will the part remaining in the desired output (ie no phase inversion) even past the +/-200mV level?

    Thank you!

  • Hi Tyler,

    Operating outside the specified parameters is not recommended. The area between the +200mV specified and and +500mV abs max is not guaranteed to function correctly - just not to cause damage.

    We cannot encourage use, or provide test results, outside of the specified parameters. Most likely it will work fine, but, again, we cannot guarantee. You would be operating at your own risk. Obviously, we would recommend staying within the  datasheet limits.

    Yes, you could current limit the diodes to stay lower on the diode IV curve, but we still would not guarantee proper operation if over 200mV beyond.

  • Hi Tyler,

    you can use diode clamps to the supply voltages (in combination with a suited current limiting resistor) and after the diode clamps divide the input voltage down by a factor of 3. Assuming a Schottky diode clamp this will limit the input voltage to within the common mode input voltage range of TLV3201.


  • Hi Paul - thank you very much for the responses. I think this answers the questions I have on this part.

    Thanks again for the help!

    Thank you very much for your response!