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TL082-Q1: Abnormal voltage drops during the operation amplifier power-on

Part Number: TL082-Q1
Other Parts Discussed in Thread: TL082, OPA627, TLV9352, TLV9352-Q1

Hi everyone,

    As shown in the figure below, an abnormal phenomenon was discovered when the Inverting Amplifier Circuit was observed.

    I want to know what the solution is to this phenomenon.In addition, what happens if the VGL and VSN are powered on at the same time.

    Thank you for your answers!

  • Hello Yuqi,

    At power up, the input common mode and minimum VCC will be incorrect for a short time. During this time output may not be as expected. 

    VGL and VSN can power up at same time, but proper supply and input common mode voltages must be present for proper op amp operation.

  • Hello Ronald,

        Thanks,I would like to know if there have any solutions to reduce unexpected output.

    Kind Regards

  • Hello Ronald,

        Thanks  for your answer.I don't understand the proper supply and input common mode voltages. Could you please explain it in detail? How should I design it.

    Kind Regards

  • Hi Yuqi,

    I don't understand the proper supply and input common mode voltages.

    The input voltage must always stay 4V away from the supply rails. This is also valid during power-up and power-down. But when applying -30V to the input of your circuit while the supply voltage is down or partially down, then you violate this specification and the OPAmp does not behave properly.

    Also, the OPAmp needs a minimum supply voitage of +/-5V to work properly. With lower supply voltages the OPAmp is out of regulation and you will see eroneous output voltages. You may want to have a look into the datasheet of TL082 for further details which seem to be missing in the datasheet of TL082-Q1.

    I would like to know if there have any solutions to reduce unexpected output.

    Applying an input voltage while the supply voltage is down is no good design practise. I would add a diode clamp to the supply rails. In an inverting amplifier as yours I would use a diode clamp between the inputs of OPAmp. See figure 33 of datasheet of OPA627. But please decrease R4 to zero Ohm then. Since the TL082 has a FET input stage, the input bias currents are very low anyway and an input bias current cancellation resistor (R4) is not needed. Also, R4 would not have any benefit since there's almost no difference between the input bias current and input offset current of TL082.


  • Yuqi,

    TLV9352-Q1 might be better. It can run on lower voltage and has a wider input common mode range. It is phase reversal resistant which is useful if negative input exists before power up. TLV9352 might have an internal power on reset which could make a negative pulse that you are trying to avoid. 

    Can you make positive supply come on before negative supply?

    Last idea is a time delayed switch on output.