ALM2403-Q1: Overvoltage protection for ALM2403Q1 output shortcut to 36V

Hi Jin,

Jin Huang said:

2. and the power dissipation at the R7 would be very high --> 5W~7W

There should be a compromise for the R7 value. If the resolver driver is shorten to 26Vdc or Vbat, then the following configuration may be used. 

If the system is required to have further protection, then you may try the following configuration. Yes, 20Ω resistor will dissipate good amount of heat. 10Ω or similar may work better. This resistor is only work when there is DC short. In a typical operation, the 10uF impedance is parallel with 20Ω, which is (1/sC)||20Ω or 0.61Ω at 10kHz.

ALM2403-Q1 26Vbat fault conditions 05152023.TSC

Jin Huang said:

The Phase margin is 124.17 (or -235,85??), so I believe with 20k R7 is no problem, is there anything error in my design??

Can you confirm the resolver load or the load you are using in the model? Typically, there is winding resistance, 20Ω (a bit low, but is possible), inductance of 1.7mH (20 + j107 at 10kHz) and parallel winding capacitance. There may be power factor correction involved, if you want to reduce the apparent power in the driver (real and reactive power), result in driving close to resistive load. Please let me know the load parameter, and I can run the AC analysis for the system.   

Best,

Raymond

Hi Raymond

Thank you very much at first!

We need a OVP up to 36V, so the 26V solution cant help us.

I just measured the Resolver with LCR meter (Keysight U1733C), here is the info of primary winding:

R_DC = 20.13 Ohm,

L@10lhz = 1.877mH

Z@10kHz = 120.63 Ohm 

The Capacitor looks a little strange:

C@10kHz = -137nF

A additional Info to the circuit plan above:

The R2, R10 and C6 (in blue circuit) belong to the load compensation in my application,  only the R5 and L2 simulate the resolver load.

That means the parameters in my simulation match the resolver feature.

What do you think?

BR

Jin

Hi Jin, 

Jin Huang said:

We need a OVP up to 36V, so the 26V solution cant help us.

Based on the 36V battery short simulation, the fault protection scheme should work, though you may place resistor and TVS in series, if one is unable to dissipate the amount of heat during the 1 mins short circuit test. 

Jin Huang said:

C@10kHz = -137nF

The simulation is ignoring the winding capacitance. It should be fairly low at approx. a few nF or lower. 

I simulated the driving circuit without the snubber circuit, the phase margin is approx. 60 degree, which it should be stable. When the loop gain cross 0dB, you will need a minimum 45 degrees phase margin to be stable. 90 degree phase margin would be the best case scenario for the loop stability. You can gradually introduce R and C across the snubber and you will see the effects. The phase margins beyond 90 will not be stable. Since this is inverting input op amp configuration, the phase margin should remain approx. 180 degrees from the input signal, which is shown in the phase diagram of the bode plot. 

I do not place snubber circuit in the stability simulation generally. The snubber Rx &Cx parameters are typically empirically determined. I normally do not use them, unless you want to dampen something in a control circuit at a specific frequency by shorting the Cx capacitor and place Rx in parallel with a load. It will also drain the excessive power to the driving circuit. 

ALM2403-Q1_MFB AC Analysis E2E-1 05162023.TSC

Here is TI reference of the Stability Reference Method, which is alternative method to the technique Marek used in your other reply. So do not get confused when we are using different AC injection techniques. 

Without knowing your driving requirements, here is something that I would recommend. 

Our resolver drivers are ALM2402F-Q1 and ALM2403-Q1, there are pros and cons in selecting one of them.  Since I do not know the application application voltage swing requirements, I am unable to comments. For Vs below 16Vdc, we would recommend ALM2402F-Q1. For higher Vs voltage up to 24Vdc, we would recommend ALM2403-Q1. 

The loop stability is the last thing we would resolve in a design. For given requirements, we would do the following:

1. Select one of resolver drivers (though we have other power amplifiers that will work for the application as well). 

2. Simulate the resolver's output swing vs. input signal (PWM sinusoidal, sine input etc.), determine gains, excitation frequency, BW, output voltage swings, current swing etc. per a design requirements.

3. I would recommend to check for heat dissipation for the part over the temperature operating range, specifically the worst case scenario, say 85C or higher, which it will involve the heat test in a thermal chamber. 

4. When driving resolver or transformer, there is power factor consideration in a design, which is to minimize the power dissipation at the resolver driver. If the driver has to deal with large level of apparent power, then the power amplifier may require to drive higher current, increase the unnecessary heat dissipation. 

5. Lastly, I would check for the loop stability and try to make sure the system is stable over operating conditions. if not, try to compensate the driver to eliminate the instability conditions.

We also have EVMs for both resolver drivers, and you can check it out the application while going through the above steps in parallel or some kind of iteration in a systematic design approach. 

https://www.ti.com/lit/ug/sbou227/sbou227.pdf?ts=1684257119244&ref_url=https%253A%252F%252Fwww.ti.com%252Ftool%252FALM2402FQ1EVM

https://www.ti.com/lit/ug/sbou236a/sbou236a.pdf?ts=1684238048947&ref_url=https%253A%252F%252Fwww.ti.com%252Ftool%252FALM2403Q1EVM%253FkeyMatch%253D%2526tisearch%253Dsearch-everything%2526usecase%253Dhardware

Please let us know if you need further assistant. 

Best,

Raymond

Hi Raymond

Thanks a lot for your answer.

I still have 2 questions.

1. about the phase margins

Raymond Zhang1 said:

The phase margins beyond 90 will not be stable

That's means a phase margin of 124.17 in my first post is unstable?  But in another post "ALM2403-Q1: power dissipation minimization, is it necessary? " I didn't see this rule, a system with phase margin of 138 degrees still very stable, could you please confirm this?

2. about the OVP design,

what if I just use 20k instead of 20Ohm, then I don't have the problem of power dissipation on the 20Ohm.

So what do you think, could I really use this design?

BR

Jin

Hi Jin, 

Jin Huang said:

That's means a phase margin of 124.17 in my first post is unstable?

The phase diagram should start off at approx. 180 degrees, you ended up with ~124 degrees, which it should not be stable. Note, this is 20Ω||1uF in the feedback loop. 

With 20kΩ||1uF, the phase started off at -165 degree at 10Hz, and ended up -235 degrees, which it has the same phase margin of 124 as shown above, and it should not be stable. 

Jin Huang said:

power dissipation minimization, is it necessary?

Yes, it may be necessary. ALM240x-Q1 family has limited output current at room temperature. For automotive application, the nominal testing temperature is 85C or higher. And the current will go down significantly as die's temperature goes up. So under the higher current resolver application, ALM240x-Q1 drivers may need to lower driving current. In addition, lower heat dissipation will prolong the life of the driver and less cooling will be required for the application.

In our other power amplifier family, such as OPA564-Q1, it is rated higher current up to 1.5A, and it can handle the higher current resolver application. In any cases, lower heat dissipation will be better options in a design, especially for automotive application. 

Jin Huang said:

a system with phase margin of 138 degrees still very stable, could you please confirm this?

Could you show me the example of 138 degrees of phase margin? The figure has to be in context where the phase level of the start point is.

Jin Huang said:

what if I just use 20k instead of 20Ohm, then I don't have the problem of power dissipation on the 20Ohm.

Do you mean 20kΩ||1uF configuration? at 10kHz, the impedance will be approx. 15.9Ω||20kΩ or ~15.9Ω. You resolved the Vout shorted to battery issues, but 15.9Ω*150mApk = 2.39Vpk drop across 15.9Ω||20kΩ within the feedback loop, and the heat dissipation will be 0.15^2*15.9 = 0.36W on the ceramic capacitor, which it will put a lot of thermal stress on the component. There should be a compromise in the design. 

If you have additional questions, please let me know. 

Best,

Raymond

Hello Raymond

Thanks again for the reply.

1. To your question:

Raymond Zhang1 said:

Could you show me the example of 138 degrees of phase margin?

here ist a result form your TI college in my other post:

Doing so shows the actual phase margin of 138 degrees - see below.  The effective load is virtually purely resistive at 10kHz.

Conducting a transient analysis shows a very stable system with the small-signal overshoot of just 10% - see below.

2. my configuration 20k // 10µF

Sorry , I wrote the wrong value (20k // 1uF) in last simulation file, 

Simutlation with the snubber circuit, see below:

Simutlation without the snubber circuit, as you suggested before, see below:

So if i simulate without snaber circuit then the result shows stable. Does this mean, the snubber circuit makes the system instable?

3. Disspation under configuration 20k // 10µF

at 10kHz, the impedance will be approx. 1.6Ω.

1.6Ω*150mApk = 0.24Vpk drop across 1.6Ω||20kΩ within the feedback loop, and the heat dissipation will be 0.15^2*1.6 = 0.036W on the ceramic capacitor.

So I think with this Configuration (20k // 10µF) I resolved the Vout shorted to battery issues and also the heat dissipation, the system looks stable (without snubber) too.

What do you think?

BR

Jin

Hi Jin, 

I will get it back the rest of the inquiries tomorrow. 

BTW, I am unable to generate this bode plot. It looks like that the bode plot may come from a different simulation circuit. 

Jin Huang said:

3. Disspation under configuration 20k // 10µF

1.6Ω impedance at 10kHz seems to be ok. Did you have a chance to try in the resolver driver? I think that it should work. 

Best,

Raymond

Hi Raymond

Raymond Zhang1 said:

BTW, I am unable to generate this bode plot. It looks like that the bode plot may come from a different simulation circuit.

I just add my Tina file here, maybe you can try it again.

ALM2403-Q1_MFB_C2_with_snubber.TSC

Raymond Zhang1 said:

Did you have a chance to try in the resolver driver?

Yes, I tried the resolver driver with 10uF//20kΩ, it works, only one problem, we can see a little distortion,  see my Oszi foto below:

BR

Jin

Hi Jin, 

Jin Huang said:

it works, only one problem, we can see a little distortion, 

I see the distortion. I think that you may need to increase to supply rail from 12V to slightly higher rail, say 15Vdc. What is your DC bias voltage as shown below? It should be configured in the mid supply rail or 6Vdc if you are using 12Vdc. 

ALM2403-Q1 has larger voltage drops across the Mosfet output stage vs. ALM2402F-Q1, when the driving current is increased. I think that the distortion is likely related to the supply rail. Likely, it is not related to 10uF//20kΩ.  

I will get the rest of your inquiries later today. 

Best,

Raymond

Hi Raymond

Raymond Zhang1 said:

What is your DC bias voltage as shown below? It should be configured in the mid supply rail or 6Vdc if you are using 12Vdc. 

Indeed, I use 6V bias and 12V Supply.

Raymond Zhang1 said:

it is not related to 10uF//20kΩ.  

I just reduced the amplitude of input signal, the distortion is still there, why?

BR

Jin

Hi Jin,

Jin Huang said:

BTW, I am unable to generate this bode plot. It looks like that the bode plot may come from a different simulation circuit.

I figured out what is going on. You were using the PSpice model dated in 2020, while I was using the latest PSpice model, published in 10/12/21. There are some discrepancy between two pspice models, that is why I am unable to get what you presented. Please download the latest PSpice model in the future, when you are performing any simulation. 

(in your uploaded model, you get two different phase results if you simulate from 10 - 100MHz vs. 1-100MHz. That is why I was confused.) 

The simulation tool is unable to distinguish between positive or negative phases, so it is up to the user to make sense of it. Typically, an op amp circuit has 90 degrees of phase margin to work with because of the presence of the dominated pole in Aol. At the input of the inverted op amp, the circuit had only 180 degrees remaining, where the circuit's output phase is already inverted by 180 degrees.  

In the case above, the AOL dominant pole occurs fp1=~100Hz, the phase changes are compensated by fz1, the phase boost by fz2 is brought down by fp2 (near no phase change at this point), before finally fp3 becomes a dominant pole rolling off gain at a rate of -20dB/decade (causing -90 phase shift) before fp4 pulls it further down to 60 degrees phase margin, which this is your phase margin result. 

(Note: phase changes are occurred at approx. 1 decade (~5.7 degree) ealier of the pole's frequency, and ends at  approx. 1 decade after the pole's frequency (~84.3 degree).  

Let us use the latest pspice model as the reference for comparison(compare apple to apple). I did change 20Ω||10uf, but it should not affect the AC analysis, and the phase plot is started at +180 degrees from the low frequency. From the bode plot, I am getting a phase margin of 75.4 degrees ( 20Ω||10uf should have little effects vs. 20kΩ||10uf, except with how the phase is started at low frequency or 10Hz by the phase diagram. I am not fully understood how the simulation tool is calculating the starting phase shift in an op amp circuit, but I know that the tool is unable to distinguish positive or negative phase shift). 

By changing the 20kΩ||10uf, the phase plot started at -180 degree at low frequency (it shifted the phase by -180 degree at the low frequency). From the phase margin, you may call the the phase margin at 102.5 degrees (-180 - (-282.46) = 102.46 degree) or 360 + (-282.46) = 77.54 degree. I typically called the latter as the phase margin to align with the plot above. 

So the previous simulated 124 degrees is equivalent to 56 degrees. Below is the copy of the simulation file. 

ALM2403-Q1_MFB_C2_with_snubber New 05232023.TSC

Please let me know if you have additional questions. 

Best,

Raymond

Hi Raymond,

sorry for my late reply, I counldn't  test it early, 

1. Issue distortion

Raymond Zhang1 said:

Also, can you try low ESR 10uF and see if there is anything related to it? 

I just changed to another low ESR capacitor (Typ: C3216X5R1H106K160AB), the disortiong is still there, look my result below:

1a. at low amplitude setting:

1b. at high amplitude setting:

Raymond Zhang1 said:

However, if you wait longer duration, say a few minutes until the current going through the 10uF capacitor are equalized, then the distortion may get less (try with 20kΩ setting over longer time, my speculation)

unfortunately i didnt see this effect.

Raymond Zhang1 said:

The simulation is shown that the R may have to drop to approx. 1kΩ range, where the distortion is not noticeable

I will try this next week than report you the result.

2.Issue OVP

I tried this configuation (20k // 10µ + TVS 26V to VCC)  with 32V at output of ALM2403, 2 different results below:

• If i connected everthing at beginning, then the IC survived.
• If i connected the 32V to the output under "hot plug" condition, then the IC damanged immediately .

I checked the IC and found, the PIN 3 (OTF/SH_DN) was always low.

I guess the suddenly applied 32V at the output went through the 10nF and the 26V TVS cant clamp it to 26V, the caused the Damage of ALM2403.

What do you think?

BR

Jin

Hi Jin,

Jin Huang said:

1. Issue distortion

I did not foresee the 20k // 10µf issues until I see your distorted scope shot. The inner loop's response has to be faster or equal to the outer control loop in frequency. The R and C will create phase shift if the time constant is high. with 20Ω // 10µf recommended in the application note, that distortion is not noticeable or not present. If you try 1kΩ // 10µf, the distortion is probably still there, and you may consider to check with FFT or spectrum analyzer. 

Jin Huang said:

2.Issue OVP

Everything fault protection methods have its pros and cons. Below is the method that is recommended for powerline communication output. 

If you concerns about Vbattery short, the simple way is to couple the resolver with ceramic capacitors, which it should block all DC short events. Please let me know your design requirements, perhaps we can find a better and cheaper way to pass these tests. 

Because the application is driving a transformer, so use capacitors to block DC battery short will work well, and it does not affect the resolver's performance, which is operating at 10 kHz or similar. So you may also consider this option. 

In order to protect ALM resolver PA drivers, you have to consider overvoltage and/or overcurrent under the transient or fault events. If you have protection circuitry against either conditions, and it is still able to meet the operational requirements, then the protection schemes will be good. 

Please let me know your testing results. 

Best,

Raymond

Hi Raymond

thanks a lot for reply.

1. Issue distortion

Raymond Zhang1 said:

If you try 1kΩ // 10µf, the distortion is probably still there, and you may consider to check with FFT or spectrum analyzer. 

With 1k // 10µF, low amplitude setting, I didn't see any distortion, see below:

1k//10µF, high amplitude setting, then I saw the distortion again:

and the FFT analysing 

Raymond Zhang1 said:

the simple way is to couple the resolver with ceramic capacitors, which it should block all DC short events.

I tried with 10µF in loop, without any resistors (instead of 1k//10µF), then I didn't get any signal. Why? 

2.Issue OVP

Our requirement: the EXC output should be protected against a short to 36V DC for 60s.

Now I used a TVS 20V instead of TVS 24V, then it works now.

So the soluttion looks like: 1k//10µF + TVS20V, and the small distortion need to consider, what does it mean to the resolver signal.

BR

Jin

Hi Jin, 

Jin Huang said:

I tried with 10µF in loop, without any resistors (instead of 1k//10µF), then I didn't get any signal. Why? 

You need to DC biasing for the feedback. Without the 1k resistor or similar, you do not have DC biasing voltage in the feedback loop anymore, which the op amp is not going to work. 

Jin Huang said:

1k//10µF, high amplitude setting, then I saw the distortion again:

at high amplitude, please check if it is resulted from supply rail. If you Vout's amplitude is lowered to 8-9Vpk and still see the distortion, then it is not due to the output amplitude voltage hitting close to the supply rail. ALM2403-Q1 has large IR drop across the mosfet driver when the output current is higher. 

Regarding to FFT analysis, I do not have the plot from the sine reference input. If you compare both graphs, you will see if additional harmonics that are generated from the reference signal, Please use or the harmonic peak ratios for comparison. From 12.5Vpp sine signal, it looks symmetric. 

Jin Huang said:

So the soluttion looks like: 1k//10µF + TVS20V, and the small distortion need to consider, what does it mean to the resolver signal.

This means that you may have a stable system to drive the resolver.

Maybe I misunderstood your question. Do you mean that what if the small distortion is present in the resolver's excitation driving frequency? --> You should remove any distortion as much as possible. Because this will result an phase errors when the angular rotation is being calculated. Typically, the firmware is calculating the phase angle at the peak of sine/cosine waveform, so you need to be watch for the distortion issues. If 1k is still not good enough, you may go down somewhat. I am not sure that it can be calibrated out (if the excitation has the distorted waveform, I am not sure that sine/cosine receivers will have the same amplitudes).   

It seems that you'd like that ALM2403-Q1 is directly coupling with your resolver. Now you need to check if the circuit is able to drive the resolver at the worst temperature conditions. In addition, there should not be large DC differential delta present between the input of the transformer. The differential dc voltage should be < 100mV or lower the better, and it does not change over temperature. DC differential voltage may result the magnetic saturation of the resolver, which you need to take a look at its datasheet and understand the specification (you need to prevent the resolver's magnetic saturation at all cost). 

Also, you need to verify the AC loop is stable over temperature as well. If it is stable at -40C or 85C or similar, then the loop stability confidence should be high or no issues. 

While doing the high temperature evaluation, you need to monitor the ALM2403-Q1's temperature that interfaced with PCB. I can simulate the power dissipation at room temperature, and estimate the junction temperature at the worst temperature operating point, when resolver's the L, C, and R parameters are finalized. 

Please let us know if you have additional questions. 

Best,

Raymond