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OPA857: What to do with the IN pin in test mode?

EnPa
Prodigy 40 points
Part Number: OPA857

Dear E2E team

I'm trying to evaluate an OPA857 using its built-in test block. This is the circuit I built:

For the first test I closed J2, pulling so TEST_SD to GND. JP1 was open, so IN was floating.
Under these conditions I was not able to get an output from the device. Both OUT and OUTN were stuck at 5/9 of the supply voltage.

When I closed JP1, connecting the photodiode to the input of the device, I started seeing something at the output (depending on the incident light on the photodiode).
It looks like some input is needed on the normal IN pin even when in test mode.

Re-reading the datasheet I found that I might have misinterpreted it. Quoting from page 17:

Set an adequate dc voltage at the input to make sure that the output is operating within normal operation.

The input mentioned here is pin IN or pin TEST_IN?

Is it normal not to see any variation a the output when operating in test mode with pin IN left floating?

If not, what else could cause this behaviour?

Thank you, Enpa

  • 0
    TI__Mastermind 25735 points

    Hello Enpa,

      Your understanding of the datasheet is correct. The quote from page 17 is referring to a DC bias at Test_IN if you are wanting to use the OPA857 in Test mode.

      The OPA857 EVM outlines and explains the test procedure for this device in detail compared to the datasheet:

         (From OPA857 EVM User Guide)

           (From OPA857EVM-978 User Guide)

       If possible, please follow steps outlined from above snippets, and let us know if you are able to see an output in device test mode. Also, feel free to ask for any further clarification on the above steps. 

    Thank you,

    Sima