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INA185: INA181, INA213-C, and INA351 - Specifications and Selection for Cost-Optimized Designs for CT as well as 4-20mA measurement circuits

Part Number: INA185
Other Parts Discussed in Thread: INA351, INA181, , INA281, INA213, INA191, INA190

Dear Community,

We're working on 2 highly cost-sensitive application use cases where we have to measure the voltage drop across a Resistor connected in series to the analog signaling circuit. Both Signaling circuit & the measuring circuits have separate grounds & potential voltages.

Accordingly, based on our initial research so far, we are exploring the TI-suggested Current Sense Amplifier (CSA - INA181, INA185, INA213-C) and Instrumentation Amplifier (IA - INA351) for their cost-optimized, higher accuracy with reduced footprint & overall solution size. We have queries regarding the interpretation of datasheets and suitable selection.

Our Queries:

Datasheet Specifications Interpretation - Typical or Maximum?

In INA181's datasheet, should we consider Typical or Maximum values for cost-optimized designs?

The low-probability extremes of OpAmp Input Offset Voltage are -280µV to 240µV in the graph published in the datasheet & do not match the stated ±500µV maximum offset limit. Similar is the case with Gain Error values. Are we missing something in our interpretation here?

What to refer to for our use case where cost-optimized selection is the key?

Potential elimination of Offset Voltage Error with Zero Reference Calibration:

Can implementing single Zero Reference Calibration across the AFE signal chain minimize offset voltage errors device-to-device? How much error reduction can be expected in practical circuits where the ADC input is a Unipolar positive range of 0-3.3V?

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Now kindly consider the following use cases:

4-20mA Receiver Circuit:

System specifications:

  • Current: 4-20mA (Unipolar DC waveform)
  • Voltage:
    • Current Loop: 0-36V (0-24V acceptable)
    • Measuring circuit: 0-3.3V
  • BW: 1kHz maximum
  • Shunt resistor: between 0.5mΩ to 160Ω
  • Error budget: 0.2-0.4%

If opting for INA213-C (improved Offset & Gain errors wrt to INA181), are these error calculations correct?

Key Error budgeting:

  • Gain Error:
    • 0.02% (Typical),
    • 0.5% (Maximum)
  • Offset Voltage:
    • ±5µV (Typical),
    • ±100µV (Maximum)
  • Post Zero reference calibration:
    • Total Error: ~0.1% to 0.75% (mostly dominated by Gain Error)

Selection of Devices - INA213-C vs INA185:

Are INA213-C and INA185 suitable choices considering they're budget-friendly with better performance (of Voffset & Gain Error) compared to INA181?

Current Transformer Design:

System Specifications:

  • BW: 1kHz,
  • CMV: <5.5V,
  • Current: 0-30mA (Bipolar AC waveform),
  • Burden Resistor: 0.5mΩ to 50Ω
  • Error budget: 0.2-0.4%

Considering INA181, INA185 & INA213-C. Is INA351 suitable for measuring CT's Burden Resistor Voltage drop, assuming Voffset is minimized by Zero Reference Calibration? Is there a parameter overlooked while evaluating INA351?

Additionally, can INA181 handle a secondary side AC voltage signal swing of +/-160mV given its CMV of -0.2V to 26V and input Voltage of 2.7 to 5.5V (positive)?

Vsense circuit when measured across terminals of Shunt resistor:

This design however seems too simplistic for robust industrial use cases.

We would like your insights & support for the impact of ESD TVS diodes as well as RC-LPF on the input side of this circuit on the stability of the overall Amplifier circuit.

We look forward to your advice and guidance.

Regards

  • Hello Valued Engineer,

    I am looking this over and will respond shortly.

    Sincerely,

    Peter

  • Hello valued community member,

     

    While the input offset will be close to the typical specification in most cases, initial input offsets (Vosi) within the limit specifications (maximum and minimum) cannot be guaranteed because these specifications are what used to screen out devices. These limits help ensure device yield and keep cost low.

    The distribution in Figure 1 does seem to show that 500uV input offset seem impossible, but the center of this distribution could shift over process and/or lot variation.

    When calculating the worst-case error, you should always use the maximum limit specification to ensure robust design. However, you can confidently use an RSS calculation as opposed to a total error calculation. RSS = SQRT( eVosi^2 + eVos_other^2 + eGain^2 + eOther^2). The reason you calculate error like this is because the chances of having a device with Vosi approaching +500uV and also having +1% gain error is extremely improbable given that 500uV and 1% gain error > 6 sigma.

    Lastly, for any error analysis, you need to focus on what the error could be at the smallest current that needs to be measured (error is dominated by offset at the smallest sense currents). Thus, it is important to know what the maximum allowable error is at the smallest current that needs to be sensed. As long as you can achieve error at this level, then you can most likely achieve error at the full scale load.  Please consider watching our training videos on how to calculate error for current sense amplifiers (and most other amplifiers).

    https://www.ti.com/video/series/precision-labs/ti-precision-labs-current-sense-amplifiers1.html

    You can absolutely calibrate out offset error (eVosi) with a one-point calibration procedure. You simply measure the Vout when load = off or load=some accurate load and put the measured offset into system memory. You then subtract out this offset from all subsequent measurements. Keep in mind that offset calibrations only negate the offset for the device at a single Vcm, Vs, and temperature. Offset errors from CMRR, PSRR, and temperature drift still remain. One important thing to know when performing this calibration is that Vout must be within the linear region (OUT wrt GND > 100mV). So it may be extremely helpful to provide a small voltage (~100mV) to REF pin, so when load=off, Vout = 100mV. At this point I recommend making output measurement with respect to REF so you negate out any tolerance error in the exact voltage at REF pin. Here is an application on driving REF pins.

    https://www.ti.com.cn/cn/lit/an/sboa551/sboa551.pdf

    Yes the INA181 can handle an oscillating input Vcm of +/-160mV, but if frequency of this is too high, then it may introduce some AC CMRR offset. Vos_cmrr_ac = (320mV)*10^(-cmrr/20dB) (note this is output referred).

     

    Considering the “Vsense circuit when measured across…”, this looks like a potential circuit for an operational amplifier (OPA). If using current sense amplifier (CSA), I would simply just insert the shunt resistor in series with signal current and measure directly. The CSA is nice because you can measure the current at a wider Vcm range that is independent of Vs.

    Given that you need a post calibration error < 0.75%, you will want to minimize device gain error because shunt resistor tolerance could easily reach 0.5%. Thus, INA185 and INA213 are going to be good options. Other options are INA281 and INA191.

    As for input ESD TVS diodes, these are only necessary if you think there could be large input voltage transients that exceed 26V. For negative Vcm spikes (< -0.3V), then input resistors can help reduce the resulting input current. For these cases, consider a device with negative Vcm rated or using large input resistors (~500Ohm to 1kOhm) and the INA190/INA191.

    Input differential filters are necessary if you think there is significant current noise. It is a good idea to place SMD pads there for it to test with prototype and take it out if it does not seem necessary. As noted in datasheet, try to not exceed 10-Ohm input resistors (Rf) for INA213 or INA181. If there is significant line current noise, the INA190/INA191 are good options because you can place input resistors up to 500-Ohms with little impact to device gain error. The benefit is that you can reduce the necessary size of the differential input capacitor (Cf) and achieve same cutoff frequency (fc = 1/(2*PI*Rf*2*Cf). Another benefit of INA191 is that offset is so low you probably would not need to perform offset calibration.

    All of this applies for any common-mode voltage noise/spikes. For this type of noise, you add common-mode input capacitors (Ccm) at input pins IN+ and IN-. However, if you add Ccm capacitors, then you need to add a Cdiff that is > 10*Ccm so Vsense remains stable during Vcm transients. You can refer to this video and presentation on how to calculate input resistance error for CSAs.

    https://www.youtube.com/watch?v=hLGN_wl-xgA

    Sincerely,

    Peter