• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 2 answers
  • Subscribers 47 subscribers
  • Views 259 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

INA200: INA200 output capload and phase margin

David Qin
Prodigy 20 points
Part Number: INA200

Hi teams,

       I have an issue about amp in INA200.

      There is the schematic.VCC is 18V, Vshunt is about 13mV. There is a 47nF cap connected to Amp out.

      When  the circuit work, output of amp(Pin 2) is a triangular wave, freq is about 50kHz and Vpp is about 700mV.

      The freq and Vpp vary with the value of cap(C1).

      Then I take off the 47nF cap or change the R1 from 0Ω to 100Ω， this circuit works well.

     Some expert say the amp load cap couldn't exceed 10nF.

     I want to know the internal mechanism and how to calculate this chip's phase margin.

     Thank you so muck.

      

  • 0
    TI__Mastermind 31565 points

    Hello Appreciated Engineer,

    Welcome to the forum.

    Calculating the phase margin (PM) for a system requires knowing when the system's loop gain = -1 or 0 in dB.

    For a closed-loop amplifier like INA200, the closed loop gain function = Acl = Aol/(1+AolB) where Aol is the open loop gain of internal amplifier, B is the feedback factor, and AolB = loop gain.

    You can graphically determine where AolB = 0dB by noting when Aol (in db) and 1/B (in dB) intersect and this happens when system Acl starts to fall off, or essentially at the device's -3dB bandwidth.

    So the easiest way to measure phase margin for the closed loop device is to measure its gain and phase over frequency, find its -3dB bandwidth, then note the phase at this frequency and add 180 degrees.

    I did this AC simulation in TINA for INA200 with no load capacitance and with 1nF load capacitance and I got approximately  PM = 128.48 degrees and 32.75 degrees respectively, with gains curves that match closely to Figures 2 and 3 in datasheet. The phase margin should be better for the higher gain (as seen in Figure 2) and should accept 10nF as noted in device specification table, but a good conservative rule is that PM should be > 45 degrees to maintain robust statistical stability over device population. So a small isolation resistor should be considered.

    Sincerely,

    Peter

  • 0 in reply to Peter Iliya
    Prodigy 20 points

    Hi Peter,

                Thank you for your reply.

                I read your calculation and I know the cap(C1) is reason why my circuit can't work. 

                Can you please furture explain why my circuit finally output a triangular wave?

                And what is the relationship between cap value and oscillation freq(about 50kHz  700mV Vpp)?

               Can I simulate  this oscillation in TINA?

               Thank you.

    David

  • 0 in reply to David Qin
    TI__Mastermind 31565 points

    Hey David,

    How stable is the shunt voltage (13mV) and common-mode voltage (18V)? This could be causing enough of a disturbance to the input which then results in the continuous oscillation at output.

    You probably can't completely simulate what you are seeing. Here is what I see with a basic step response closed-loop stability test:

    I do in fact see an approximate 50 kHz oscillation (1/18us = 55.55 kHz), but it is decaying, not continuous and nowhere close to 700mV peak-peak.

    The output capacitor will in fact determine the stability and more specifically the dominant frequency component of the oscillation. This is because the closed-loop output impedance (Zout) of INA200 is inductive, so at some point there will be a resonance between the inductance and the capacitance.

    Here is a plot of the INA200 Zout. Note that at 55 kHz, the Zout is rising (inductive).

    Here is the Impedance of Zout with a 47nF load capacitor. Note the peak in impedance at 60 kHz. 

    This peak is where the falling (capacitance) intersects with the Zout inductance causing oscillation at approximately 50-60kHz.

    The bottom line. Don't load the output with capacitance unless you can place some isolation resistance to flatten the load impedance (orange curve) before it intersects with Zout. With an isolation resistance, orange curve will flatten to the Riso value chosen and by the frequency 1/(2pi*Riso*Cout)

    Sincerely,

    Peter