OPA855DSGEVM: Layout a PCB with 4 OPA855, how to handle the power plane or layers

Hi Gang Huang,

The layer stack you are implementing would be the safe route to go with. The EVM is put together with a split power plane, but this will lead to problems if trying to implement in a more involved design like yours. You will need to use vias like you mentioned, however one tip is to use multiple vias in parallel as this can considerably decrease the unwanted inductance for any pad needing to go to a different layer. Since you will be using multiple devices in your design, try to keep all your power and ground planes as uniform as possible as this will help limit crosstalk and EMI. I was also noticing the cutout of the ground and power layers for the feedback and inverting pin; it is hard to tell what is being cutout, but the goal is for the cutout to be around the FB and IN- pin. Figure 10-12 in the datasheet shows this more clearly. As for the C7 capacitor, there should not be a problem that it is overlapping the cutout however, if possible, it would be a good idea to add a few more vias to the ground pad of the capacitor. In general, to limit any parasitic capacitance we always recommend having your components as close as possible to the device and have the closest connections possible. The EVM you have been referring to will be your best asset when designing and laying out your board, but I will also attach some PowerPoints that go in depth and cover more concepts and best practices. 

TI high-speed PCB guidelines.pdf

High-Speed Interface Layout Guidelines (Rev. J) (ti.com)

Best Regards,

Ignacio

Hi Ignacio, 

Thank you for the suggestion. 

I updated the layer stack further to 6 6-layer board, and now the board looks like this, I also have the courtyard shown so you can see the cutout location. 

Would you please comment on the layout?

Thanks,

 opa855_6layer.pdf

Hi Gang Huang,

For six layers, this is the recommended stack up. I am able to see the cutouts and there are matching the OPA855EVM, which is our overall recommendation. However, for the cutout at the output pin, it seems to not align with the pad directly connected to the output pin. One adjustment I would make is to maybe add more vias where possible.  For example, adding vias around the grounds for the decoupling capacitor's ground pads would be a huge benefit. The first image circles this idea of adding multiple vias, as this reduces overall inductance. I would also suggest removing the ground via that is directly on the ground pad (second image) as this could cause the solder to want to flow into the via and may cause some soldering issues. Is the design also implementing 0402 size components? It is hard to tell but like we discussed having the layout as tight as possible is the overall goal of designing for such a fast device. This is key to limit parasitic in the layout. I would also suggest looking at the decoupling scheme used on the OPA855EVM for the larger capacitors that are meant to be farther way from the device. These also have their purpose so I would like to highlight this important layout requirement as well.

Best Regards,

Ignacio

for the cutout at the output pin, it seems to not align with the pad directly connected to the output pin.

Regarding the cutout, which one would you recommend for the IN- and OUT?

One adjustment I would make is to maybe add more vias where possible.  For example, adding vias around the grounds for the decoupling capacitor's ground pads would be a huge benefit. The first image circles this idea of adding multiple vias, as this reduces overall inductance.

I would also suggest removing the ground via that is directly on the ground pad (second image) as this could cause the solder to want to flow into the via and may cause some soldering issues.

Is the design also implementing 0402 size components? It is hard to tell but like we discussed having the layout as tight as possible is the overall goal of designing for such a fast device.This is key to limit parasitic in the layout.

I would also suggest looking at the decoupling scheme used on the OPA855EVM for the larger capacitors that are meant to be farther way from the device. These also have their purpose so I would like to highlight this important layout requirement as well.