THS4522: Sensitivity to parasitic capacitance at the output of THS4522

Hi Christian,

I assume you are referring to Sections 8.3.8 and 8.3.9 of the datasheet. In Section 8.3.8, you can expect to see some peaking in the frequency response and lower bandwidth if you are using large resistors and have a large parasitic capacitance from the PCB board. The interaction of the parasitic capacitance of the board and the device interacting with load and feedback resistors will cause a zero to form that alters the frequency response. If the capacitance is minimized and large resistors are not used, the effects of this zero will also be minimized. Here is an app note that discusses the effects of parasitic capacitance in much more detail (link). In Section 8.3.9, there is some variation in frequency response that is attributed to added parasitic elements due to device package type and layout changes to fit the specific package type.

It is hard to comment on your configuration specifically without knowing more details about what device package you are using, your board layout (to check if there could be large sources of parasitic elements), and what passive elements you are using in your 2nd order MFB low pass filter design. If you are able to estimate board parasitics, you can add this to simulation to get a better representation of how the device will behave (though that does not guarantee exact real world behavior). As always, we recommend following the layout guidelines (Section 11 in the datasheet) in order to minimize the parasitic elements to achieve best device behavior.

Please let me know if you have additional questions.

Thanks,

Nick