• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Answers 3 answers
  • Subscribers 48 subscribers
  • Views 210 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

LMP8601-Q1: Maximum Input resistance allowed at IN+ & IN- Inputs

LMP8601-Q1: Undesired voltage at input (IN+, IN-)

DEVENDHIRAN KUMARASAMY
Prodigy 110 points
Part Number: LMP8601-Q1

Tool/software:

Hi,

While testing the LMP8601x device it has been observed that IN+ and IN- pins are having a voltage of 2.5V when the current measurement inputs are left floating (i.e., without input condition).

The test setup and measurement conditions are as mentioned below:

  • VDD_5V0_VREF is supplied with 5V.
  • VPOS and VNEG are left floating or not connected with actual load setup to measure the current.
  • Voltage at IN_P and IN_N are measured at the voltage level of 2.5V.

Could you please clarify why this voltage level is appearing at the IN_P and IN_N pins after power up?

Regards,

Devendhiran K

  • 0
    TI__Expert 5250 points

    Hello Devendhiran,

    In general, floating input pins will put the voltages of our parts in an undefined state (unless the datasheet defines the parts behavior under those circumstances), so having an somewhat unpredictable voltage at the input is the expected result from your test.

    However, for this part we can actually get some intuition into the voltage level. The input bias current is the current flowing into or out of the input pins and depends on the Vcm level of the part. This will charge and discharge any capacitance you have attached to the input pins in a negative feedback loop until the current reaches the zero point shown in the Ib vs Vcm plots:

    This voltage looks lower than your measured voltage of 2.5V, probably because of manufacturing variations (I wouldn't be surprised if it varies significantly)

    Let me know if you have any more questions,

    Levi DeVries

  • 0 in reply to Levi DV
    Prodigy 110 points

    Hi,

    Thanks for your feedback.

    I have following questions related to this behavior.

    1. Does this behavior (charging of input path capacitance through bias current) happen only after power up of device?
    2. Does this behavior (charging of input path capacitance through bias current) happen every time after the applied Vin voltage is removed and left the inputs floating?
    3. If IN+ & IN- pins are connected with 100K Pulldown resistor option to GND, whether the voltage raise due to bias current flow will be eliminated?

    Regards,

    Devendhiran K

  • 0 in reply to DEVENDHIRAN KUMARASAMY
    TI__Expert 5250 points

    Hello,

    DEVENDHIRAN KUMARASAMY said:
    Does this behavior (charging of input path capacitance through bias current) happen only after power up of device?

    Yes, when the device is powered down there will be no power source for the bias current, so the only effect that can take place is the discharge of the input capacitance through the input resistance.

    DEVENDHIRAN KUMARASAMY said:
    Does this behavior (charging of input path capacitance through bias current) happen every time after the applied Vin voltage is removed and left the inputs floating?

    Yes this will happen whenever the input is left floating while the device is powered, causing the bias currents to flow.

    DEVENDHIRAN KUMARASAMY said:
    If IN+ & IN- pins are connected with 100K Pulldown resistor option to GND, whether the voltage raise due to bias current flow will be eliminated?

    The current into the pin will create a voltage drop across the 100K resistor, so the voltage will instead settle at some low voltage from around 0-500mV. This can be reduced by using a stronger pulldown resistor to reduce the voltage drop to GND.

    Let me know if you have any more questions,

    Levi DeVries

  • 0 in reply to Levi DV
    Prodigy 110 points

    Hi,

    Thanks for the detailed response.

    Is this bias current in and out flow behavior due to the reason that LMP8601x device has the level shift structure at the CSA input pins?

    If so, if we choose any other current sense amplifier which does not has this structure results no voltage raise at the inputs?

    Regards,

    Devendhiran K

  • +1 in reply to DEVENDHIRAN KUMARASAMY
    TI__Expert 5250 points

    Devendhiran,

    DEVENDHIRAN KUMARASAMY said:
    If so, if we choose any other current sense amplifier which does not has this structure results no voltage raise at the inputs?

    All of our shunt-based current sensors will take some amount of input bias current, but the amount of input current can vary significantly based on the device.

    The best way to reduce the voltage at the device inputs will be to stop floating the input voltage, either by using pull-down resistors or by keeping the input current connected.

    Let me know if you have any more questions,

    Levi DeVries

  • 0 in reply to Levi DV
    Prodigy 110 points

    Hi,

    Thanks for feedback and support.

    Regards,

    Devendhiran