TLV3801: Output polarity for wide pulses greater than 1 us

RajK

Part Number: TLV3801
Other Parts Discussed in Thread: ADS8344, OPA4277, DS25CP152, OPA189

Tool/software:

Hello,

We have a fabricated circuit with TLV3801, DS25CP152, OPA189, OPA4277 and ADS8344 (see Figure 1.). TLV3801 (Figure 2.) is being used in a non-inverting comparator configuration with below power supply voltages -

VCCI and VCCO = 4V
VEE = -1.25 V

The non-inverting input is a 1 us 3.3 V pulse and the inverting input is DC voltage controlled via a resistor divider that consists of a resistor pot. The output of the comparator is logic pulse when probed at the Positive P arm of the LVDS pair output of DS25CP125 splitter and is inverted with respect to the input pulse. This is unexpected because of the non-inverting configuration of the comparator. The output of the comparator is as expected and non-inverted when short pulses of width < 1 us are connected to the non-inverting input. This is also probed at the positive P arm of the LVDS pair output of DS25CP125 splitter and the scope is 50 Ohm terminated with DC coupling.

We replicated this configuration with TLV3801 evaluation board and could see correct output polarity w.r.t. input pulse polarity for 1 us 3.3 V pulse as well as shorter pulses < 1 us.

Could you please review the below custom circuit and recommend any changes and insights for this observed behavior, which is the output pulse polarity is inverted for wider pulses >= 1 us and correct polarity for shorter pulses < 1 us. Thank you

Figure 1: Overview

Figure 2: TLV3801

Figure 3: DS25CP152

Figure 4: OPA189

3 months ago

0 Clemens Ladisch 3 months ago

Guru 280110 points

CompOut3_P is connected to the inverting output.

If there is still a problem, please show an oscilloscope trace.

0 HO SIU 3 months ago in reply to Clemens Ladisch

TI__Expert 5280 points

Hi Raj,

Per Clemens' reply, the output of the TLV3801 seems to be inverted. The pinout for the TLV3801 has OUT+ on pin 8 and OUT- on pin 1.

In this case, the OUT+ is the node CompOut3_N and the OUT- is the node CompOut3_P which means the output would be inverted when compared to what you would expect.

I'm curious as to why the inversion is dependent on pulse width. Could you show some oscilloscope pictures as Clemens has suggested? In addition, it seems that the outputs shown are "CompOut3" while the inputs to the DS25CP152 are "CompOut1". Are the connections the same for CompOut1 as CompOut3?

0 RajK 3 months ago

Intellectual 740 points

Chuck Sins Chi Nguyen1 Clemens Ladisch HO SIU
Regarding output polarity, please find below scope traces at different frequencies. The input signal is sinewave (yellow trace) connected to non-inverting input pin and the comparator output is purple trace. A resistor voltage divider circuit is used for setting the threshold voltage on the inverting input pin as shown in Figure 2. in main post. R16 is 1 kOhm and P4 is a 5 kOhm resistor pot.
IMPORTANT NOTE - For all the test cases, the resistor pot is set to 5 kOhm. The threshold voltage is measured at the output of the unity gain buffer as shown in Figure 4. of the main post. The comparator output (purple trace) is measured at the output of DS25CP152 as shown in Figure 3. of main post

1. Signal = 1 GHz. Threshold = 0.484 V

2. Signal = 900 MHz. Threshold = 0.470 V

3. Signal = 800 MHz. Threshold = 0.450 V

4. Signal = 700 MHz. Threshold = 0.438 V

5. Signal = 600 MHz. Threshold = 0.443 V

6. Signal = 500 MHz. Threshold = 0.422 V

7. Signal = 400 MHz. Threshold = 0.414 V

8. Signal = 300 MHz. Threshold = 0.400 V

9. Signal = 200 MHz. Threshold = 0.391 V

10. Signal = 100 MHz. Threshold = 0.336 V

Q1. Why does the DC threshold voltage change with change in input signal frequency? My understanding is, it should be constant because the resistor pot is set to 5 kOhm for all test cases. Chuck Sins, you mentioned in the previous post (TLV3604: Output of TLV3604 when input greater than 200 MHz. - Amplifiers forum - Amplifiers - TI E2E support forums) about input bias current of TLV3801. Could you please elaborate on that based on these new findings and the circuit schematic.

Q2. The comparator output polarity should be same as the input signal polarity across all frequencies. The eval board output for all the above test cases is consistent and the output polarity matches the input signal polarity. However, the custom board with TLV3801 output connected to DS25CP152 has different behavior.

0 HO SIU 3 months ago in reply to RajK

TI__Expert 5280 points

Hi Raj,

In addition, how are you probing your signals IN+ and OUT? Are they with active diff-probes, single-ended probes, etc.? In addition, are the signals shown in the oscilloscope picture probed at the board, directly at the inputs/outputs of the comparator through test points?

RajK said:
Chuck Sins, you mentioned in the previous post (TLV3604: Output of TLV3604 when input greater than 200 MHz. - Amplifiers forum - Amplifiers - TI E2E support forums) about input bias current of TLV3801. Could you please elaborate on that based on these new findings and the circuit schematic.

From what I understand, Chuck was referring to the input bias current of the TLV3801, which is relatively high in the 2uA typ. range. This input bias current flowing into the input(s) of the comparator would mean that the input impedance is not infinite, meaning there will be mV of deviation in your calculated reference voltages. The resistor divider that you are using to set the reference voltage is a relatively low value, so I wouldn't expect to see the bias current to make cause deviations as large as you've observed (100s of mV)

Q2. From Clemens' and my previous reply, it seems like the mapping of the outputs is inverted so I would expect the output polarity to be inverted as compared to the input polarity across all frequencies. It seems to not be the case as shown in your oscilloscope pictures. The input and output seem exceedingly out of phase with each other. For example, it doesn't even appear the 100MHz test case switches at 0.336V. Have you ensured that the input and output oscilloscope probes have been properly time skewed to calibrate for the delay of the scopes?

I have a follow-up question as well. What is the peak-to-peak voltage as well as the DC offset of the signal generator for the IN+? It seems to me that the yellow trace goes exceedingly negative. If the VEE of the device is -1.25V, the negative trace seems to be at -2V or exceed -2V in some cases. This violates the input voltage range of the device, which is VEE + 1.5V to VCC + 0.1V. The inputs to the comparator should remain within 0.25V to 4.1V to satisfy the recommended operating conditions.

0 RajK 3 months ago

Intellectual 740 points

HO SIU
Please find the layout of the comparator below. Both the input traces are farther apart from each other (75 mil).

Below is scope screenshot for 100 MHz input signal, where the input signal is yellow trace measured with differential probe at pin 5 of the comparator, comparator output measured at output of DS25CP152 purple trace, DC threshold voltage blue trace measured with differential probe at pin 4 of comparator and doesn't look to be clean. However, when it's measured at the output of the unity gain buffer (OPA189), it looks clean. C27 is a decoupling capacitor that should decouple any AC component in the DC input signal.

Q1. How are you measuring the DC threshold voltage? Are you observing it through an oscilloscope probe? The threshold voltage trending down with the input frequency seems to point at the threshold voltage being dependent on the frequency of the non-inverting input. Perhaps the non-inverting terminal could be coupling onto the inverting terminal through some parasitic capacitance. Have you probed the threshold voltage and confirmed that it's a clean DC signal for all of your test cases?

In the prevoius reply, it was measured at the output of the unity gain buffer using a multimeter.

In addition, how are you probing your signals IN+ and OUT? Are they with active diff-probes, single-ended probes, etc.? In addition, are the signals shown in the oscilloscope picture probed at the board, directly at the inputs/outputs of the comparator through test points?

In the previous reply, IN+ was probed using differential probe at pin 5 of the comparator and OUT was probed using single-ended probe at the output of DS25CP152.

Q2. From Clemens' and my previous reply, it seems like the mapping of the outputs is inverted so I would expect the output polarity to be inverted as compared to the input polarity across all frequencies. It seems to not be the case as shown in your oscilloscope pictures. The input and output seem exceedingly out of phase with each other. For example, it doesn't even appear the 100MHz test case switches at 0.336V. Have you ensured that the input and output oscilloscope probes have been properly time skewed to calibrate for the delay of the scopes?

The inversion of the comparator output has been accounted for in the scope traces.

I have a follow-up question as well. What is the peak-to-peak voltage as well as the DC offset of the signal generator for the IN+? It seems to me that the yellow trace goes exceedingly negative. If the VEE of the device is -1.25V, the negative trace seems to be at -2V or exceed -2V in some cases. This violates the input voltage range of the device, which is VEE + 1.5V to VCC + 0.1V. The inputs to the comparator should remain within 0.25V to 4.1V to satisfy the recommended operating conditions.

The sine wave from the signal generator was 15 dBm (4 Vpp).

0 RajK 3 months ago in reply to HO SIU

Intellectual 740 points

There are multiple instances of the same comparator, DS25CP152 and OPA189 components and the circuits for them are same. Please read the signal names as CompOutX_N and CompOutX_P

0 HO SIU 3 months ago in reply to RajK

TI__Expert 5280 points

Hi Raj,

Thanks for sharing the layout. The decoupling capacitor C27 was placed some distance away from the IN- pin (Pin 4), and a relatively long trace connects the capacitor top plate to the pin. This may have deteriorated the effectiveness of the filtering capabilities of the capacitor.

Looking at the picture, there seems to be ~2-4ns of delay between the IN+ crossing IN-. This shouldn't be too unexpected if there are delay contributions from the two different probes. Could you please tell me the models of the diff probe and the passive single-ended probe that you are using?

RajK said:
The sine wave from the signal generator was 15 dBm (4 Vpp).

I'm going assume the DC offset is 0. A 4V Vpp centered around 0V would exceed the input voltage range of the comparator. Going to -2V exceeds the absolute maximums of the comparator and could result in permanent damage to the comparator:

Could you please show the device operation when both inputs are within the recommended operating range of VEE + 1.5 to VCC + 0.1 (0.25V to 4.1V?

0 RajK 3 months ago in reply to HO SIU

Intellectual 740 points

Hi HO SIU, there's an interesting behavior I came across. As the DC threshold voltage (inverting terminal signal) is increased, the comparator output shows correct behavior and its width changes according to the threshold voltage. However, as the DC threshold voltage is increased beyond 1.3 V, a DC offset is observed on the non-inverting terminal signal and is proportional to the increase in inverting terminal DC voltage. Please see below scope screenshots at different DC threshold voltages on inverting terminal.

Blue trace - Non-inverting input, pulse signal.
Yellow trace - Inverting input, DC voltage
Purple trace - Comparator output.

0 RajK 3 months ago in reply to RajK

Intellectual 740 points

The datasheet mentions "limiting the differential input voltage to be no more than twice the diode's forward-voltage drop 2 × VF (2 × 0.7 V).". This behavior is observed when the DC threshold voltage is increased above ~1.3 V, which also happens to be 2 x VF = 2 x 0.7 = 1.4 V. Could you please explain the role of the diode's forward voltage and input bias current in my circuit and possible ways to mitigate it. Our requirement is the non-inverting terminal signal will be within 0.25 to 4.1 V and the DC threshold voltage on inverting terminal will be between 0 to 2.7 V

0 HO SIU 3 months ago in reply to RajK

TI__Expert 5280 points

Hi Raj,

Yes, the DC bias that you see coupling onto the non-inverting is caused by the internal double diodes. The recommended operating conditions lists the differential range to avoid forward biasing these diodes:

The role of the diodes is to protect the input stage of the comparator. The diodes clamp the input differential to ensure that the internal nodes of the comparator maintain certain biases and prevent damage to the core of the device.

RajK said:
Our requirement is the non-inverting terminal signal will be within 0.25 to 4.1 V and the DC threshold voltage on inverting terminal will be between 0 to 2.7 V

Please note that both inputs need to be within the recommended operating range for the device to behave according to datasheet specs. The range for the non-inverting terminal will need to be from 0.25V to 2.7V if VEE = -1.25V.

Since the double diode clamps are internal to the device, the voltage across IN+ and IN- will always be clamped to 2 x VF. To mitigate this, you could do the following:

Voltage divide the inputs such that the comparator would never see a differential greater than |1.5V|. This way, the double diodes will not forward bias and cause the inputs to clamp.

Per the datasheet, you could put current limiting resistors on both inputs of the comparator. Whenever the differential becomes too large and the diodes become forward biased, the input current limiting resistor will limit the current to <10mA.

0 RajK 2 months ago in reply to HO SIU

Intellectual 740 points

HO SIU

HO SIU said:
Since the double diode clamps are internal to the device, the voltage across IN+ and IN- will always be clamped to 2 x VF. To mitigate this, you could do the following:

Voltage divide the inputs such that the comparator would never see a differential greater than |1.5V|. This way, the double diodes will not forward bias and cause the inputs to clamp.

Per the datasheet, you could put current limiting resistors on both inputs of the comparator. Whenever the differential becomes too large and the diodes become forward biased, the input current limiting resistor will limit the current to <10mA.

Thank you for your response. If we change VEE from -1.25 V to -1.5 V and VCC from +4 V to +3.75 V, what value current limiting series resistors do you recommend ?

Could you please provide an example design for the voltage divider circuit on the inputs such that the differential voltage never exceeds 1.5 V.

0 HO SIU 2 months ago in reply to RajK

TI__Expert 5280 points

Hi Raj,

You could choose from one solution or the other. If you voltage divide the inputs such that the differential between the inputs never exceed 1.5V, then the internal diodes won't forward bias to clamp the input differential. If you do exceed the differential without the voltage division, then the current limiting resistors are used to limit the current flowing through the diodes such the diodes don't get damaged. Section 7.4.1 of the datasheet details the use of current limiting resistors.

RajK said:
Thank you for your response. If we change VEE from -1.25 V to -1.5 V and VCC from +4 V to +3.75 V, what value current limiting series resistors do you recommend ?

This change would shift the common mode voltage range such that it includes GND. The diodes are forward biased based on the input differential. From the reply above, it seems like the maximum differential voltage would be 4.1V - 0V = 4.1V.

You can calculate values using KVL on this circuit:

RLIM of 1kΩ would limit the current to ~|1.2mA| range.