LM6144: LM6144 Input Bias Current

Hello Jacob,

Thank you for your feedback.

The V+ is connected at 12V and the V- is connected at -5.78V, so the Vcm range is 17.78V.

The reason why there is such a broad range is because I am using the LM6144/LM6142 in a bias circuit for a low noise amplifier which has two internal stages. for example for the first stage the gate voltage is between -5V and +7V, and for the 2nd stage the gate is between 0V and 7V. In order to simplify the design I selected the same supply for the all LM6144/LM6142 opamps.

My guess is that the input bias currents are entering into the pin, because I compared my calculations in this case with the measured output voltage and the results are closer than in the case when it exists the pin.

However, it is tricky to assume this rule for all the LM6144/6142 opamps from the DC Bias Circuit, and that's why I contacted you in order to get some help for knowing how to interpret the information from the datasheet.

Thank you,

Marius

Hello Jacob,

please see below an excerpt from the schematic:

I measured 186-188mV on the output of U1507A, but in the calculations I got 225.857mV. I considered the input bias currents for positive and negative inputs of the OPAMPs to be positive and to exit the from the device.

I considered Ibias=168.75nA, according to Figure 6, and Ios=5nA according to Electrical Characteristics. I calculated from these two values the input bias currents for the positive and negative inputs of the OPAMP.

For the offset I considered 1.2mV according to Figure 5.

I am trying to understand from where it is coming this big difference between the calculated value and the measured one.

Best regards,

Marius

Hey Marius,

Here are my thoughts:

You are effectively creating a voltage divider which feeds into a gain of 2V/V. Can you try probing at the input to each OPA and probe the output of each OPA to better understand where the error is coming from. Where is the 2.72V coming from? Is this a precise voltage?

The bias current can absolutely contribute error, but it should not be as high as you are seeing. I also get around 225mV for my expected output in simulation. 

Can you let me know what the node voltages are at U1507B and U1502B? 

Thanks,

Jacob

Hello Jacob,

The 2.72V is the output of a potentiometer that we are using to adjust the DC Bias set point. The potentiometer has one terminal connected to 5V and the another one to GND. From my calculations it is 2.717V.

Please see below the voltages at different nodes:

U1502B_pin5=2.73V   U1502B_pin7=2.73V

U1507B_pin6=0V    U1507B_pin7=-2.52V or -2.53V

U1507A_pin3=96.1mV   U1507A_pin1=181mV to 183mV

The output of U1507A calculated with these values is 218mV compared to 225.857mV that was calculated based on the datasheet information:

The voltage at pin3 of U1507A calculated based on the measured values is 109.273mV, compared to 113.16mV that was calculated based on the datasheet information:

The input bias currents that I calculated are:

The information that I considered from the datasheet:

Please see below the calculation of the input bias currents for OPAMP LM6144/6142:

From what I could see is that the input bias current value contributes to the value of the result.

Please let me know if these values/formulas are ok?

Thank you,

Marius

Hello Jacob,

Thank you very much for your feedback.

I think that I will start first with the second option, the cancelation of the input bias currents, so I think that I can apply this method on:

-  U1507B: on the positive input to have a 5K to GND

- U1507A: not necessary

- U1502A: on the positive input to have a 10K in parallel with 36K

Best regards,

Marius

Hello Jacob,

I observed a strange behavior on another circuit where I am using the same OPAMPs LM6144/LM6142. When the input voltage to the below circuit is 0V, I an see that there is present a sinusoidal oscillation with a 1V pk-pk of around 450KHz/1.22MHz on U1500C. I observed the same issue also on an older prototype board where the PCB Layout is much simpler, when I wanted to see if there could be some influence from the parasitics from the PCB layout. I suspect that there could be some parasitic capacitance on the OPAMP input that could cause this, but the problem is that I see this behavior only on the negative input.

Could you tell me please your opinion?

Thank you,

Marius

Hello Jacob,

I would like to inform you that I followed the datasheet suggestion and I added a Cf=10pF and the OPAMP looks stable now, I don't have any ringing at the negative input.

However, I would like to discuss something else with you and to get some support from you please, if it is possible.

On the output of U1500D the voltage looks as in the attached picture. The voltage by default is staying at -5.8V, which is equal with the -Vs, and once I set the potentiometer in order to get the expected DC bias gate voltage, the output of U1500D starts to increase, and reaches 1V after 28.8ms.

The time constant tau=R1506*C1504 is 5.1ms, so 5*tau=25.5ms.

Could you tell me please, is that duration of 28.8ms related to the charging time of the capacitor C1504?

If you look in one of our previous discussions you can see there an excerpt from the schematic.

Thank you,

Marius

Hello Jacob,

I am writing you regarding another interesting behavior that I observed on another DC bias circuit that uses LM6144.

In the case when the input voltage is set to 0V there is observed an offset voltage on the output of the integrator opamp of about 760mV-800mV.

This value looks strange because if there is an input offset voltage then the output of the integrator opamp should increase until it reaches the saturation (12V), but in my case it stays around 750mV-800mV.

I tried to add a resistor in the feedback loop, in parallel with C504, and I succeeded to get rid of the offset, but I lost the integration function.

Could you help me please to understand from where it could come this voltage level, and how to solve my problem?

Thank you,

Marius

Hi Marius, 

I suspect this is being caused by the OPA not having any relative DC voltage to be set to. Since there is no feedback resistor, there is no path for DC current. 

What value feedback resistor did you use? Sometimes this has to made especially high to give the OPA enough path for DC current to flow while still ensuring the integrator works in the desired frequency range. 

Is the integrator otherwise working for you?

Thanks,

Jacob

Hi Jacob,

I tried two resistor values 51ohms and 510ohms because I saw that it is recommended that this resistor should be 100 times lower than the resistor connected at the negative input of the opamp. 

What I observed is that I got rid of the output offset voltage, but the opamp is no longer working as an integrator, it looks like an inverting opamp.

Could you tell me please what value do you recommend for this resistor, and how to select it?

Thank you,

Marius

Hey Marius, 

What is your integration frequency range? The lower frequency limit will set this RF. 

51 and 510 ohm seem too low for the integrator. The goal is for the circuit to become like an inverting amplifier only at very low frequencies. It is not uncommon to see megaohms to even hundreds of megaohms as this RF for the integrator. 

Here is our circuit design guide for this exact circuit: Integrator Circuit

Once I know the lower limit, I can help calculate your ideal RF.

Thanks,

Jacob

Hello Jacob,

Thank you very much for your reply, and for the example.

The input voltage at the integrator OPAMP is not a periodical signal. Idea is that we set the bias condition at the beginning and in case the bias current changes due to tolerances, temperature drift, or aging then to readjusted.

To explain you a little bit about our unit: it is supplied from 230Vac, 50Hz, and then this voltage is rectified and with LDO's are made all the needed lower voltages from the board. Hence 50Hz, or 100Hz as it is in your example is good.

The frequency range of the low noise amplifier that we have to DC bias is from 350MHz to 1050MHz.

I hope that I could helped you. Otherwise, we could have a short Teams meeting. (marius.pop@aac-clydespace.com).

Best regards,

Marius 

Hello Jacob,

Please see the below calculations:

The minimum frequency is 33.77Hz.

Best regards,

Marius

Hi Jacob,

Firstly, I would like to share with you some highlights from today:

1. Based on the example shared with me, I did some reverse calculations in order to find the f0db for the already defined Cf, and R, and this is 30Hz.

I considered for fmin 10Hz and for fmax 100KHz. The calculated Rf should be higher than 15.915Mohms, and I measured the output of U500D considering an Rf of 16Mohm, but the offset was still present (Channel1 is U500D output, and Channel2 is the drain current of the mosfet).

The offset was present also at 3.3Mohms. I will check at 1Mohm tomorrow.

2. Based on what is written in the paper that you shared with me: " The integrator circuit outputs the integral of the input signal over a frequency range based on the circuit time
constant...", I did some calculations:

Considering an Rf of 110Kohm, or 100Kohm solves the problem of the offset:

110Kohm:

100Kohm:

I observed that for Rf=10Kohm the integration function is lost:

When Rf is increased to 25Kohm it starts working as an integrator, but it is observed that he drain current is smaller:

Please let me know if the calculations are ok.

Could you tell me please how do you know that Rf should be between 500K and 1M? I will test it tomorrow, but I am very interested to know how you estimated.

Thank you,

Marius

Hello Jacob,

Please see below some measurements based on your recommendation 500K -1M.

Rf=1M

Rf=500K

Rf=200K

Rf=100K

What I observed is that the drain current amplitude is somehow related to Rf, and starts to decrease when Rf decrease:

Rf 1M   Id=118mA

Rf=900k  Id=118mA

Rf=800k  Id=118mA

Rf=700k  Id=118mA

Rf=500k  Id=115mA

Rf=300k  Id=114mA

Rf=200k  Id=110mA

Rf=100k  Id=100mA

On one hand I get rid of the output voltage offset, but on the other hand I get a lower drain current.

Could you tell me please, why is this happening, and how could I be sure that the opamp is still working as an integrator?

Thank you,

Marius

Hello Jacob,

I think that I have a last topic to discuss with you regarding my circuit that is using the LM6144.

I am using the below circuit to control the gate of the FDN337N MOSFET, where U1500 is a LM6144, and U1502 is a LM6142.

The reason why I am writing you is because I have some issues in estimating correctly the output voltage of U1500D (voltage on pin 14), the one that is applied on the FET gate. I tried to replace in my formula the measured values of Vo_U1500C and Vo_U1502A but still I am not able to get the same U1500D output voltage as the one that I measured.

So, could you help me please to understand what I did wrong?

The formula for calculating the output voltage of U1500D is shown below, it includes the influence of the input DC offset and of the input bias currents:

The result with the replaced measured values:

Measured Vo_U1500C:

Measured Vo_U1502A:

Measured FET_drain_current:

Measured Vo_U1500D:

Thank you in advance,

Marius

Hi Jacob,

Please see below the C1504 value calculated considering all the tolerances.

Could you tell me please what do you mean by pin 13 of U1500D to stay close to GND during the measurement?

When I measured the voltage on pin 14 of U1500D, the GND was taken from a place from the board, from the screw hole.

Best regards,

Marius

Hey Marius, 

Thanks for confirming the capacitor you are using, this helps me understand where this error could be coming from.

I am interested to know if pin 13 is changing voltage much during the integration:

The capacitor can certainly influence the error here, but your calculation shows it should not be changing the slope of the integration as much as we are seeing. 

This means we need to start looking at the current charging C1504. This current will derive from the voltage drop across R1506 and R1508. Ideally, pin 13 should be the offset voltage of the device: very close to GND in this circuit. 

The thing which confuses me, it sems we are getting more charging current than we are expecting from calculation and simulation. I do not know why this would be. 

IIB will contribute a relatively small amount of error as we should be talking about integrating close to 170uA of current at time = 0ms. 

Hi Jacob,

Please find below some measurement results:

- U1500D output voltage during integration:

-U1500D pin 13 voltage during integration (as you said it is 0V):

- C1504 current during integration (almost 0A):

- MOSFET drain current during integration:

- MOSFET drain voltage during integration:

Please let me know if you need something else in order to be able to find from where is coming the difference between the measured and the calculated value of the integrator opamp.

If there is done a reverse calculation starting from the measured values of the output voltages of U1500D, U1500C, and U1502A (shared with you in the previous message) it is observed that C1504 value is no longer 100nF, it is around 2.28nF - 6.7nF. 

I am wondering what is causing the change in value of C1504? Regarding the formula I think that it is correct, right?

Thank you,

Marius

Marius,

Thanks for taking the screen shots, I still cannot find why this is not working.

I like the idea of working backwards. 

Yes your equation is correct, I get the same expression when I break everything out. 

When I plug in numbers, I am not using -4.6V for Vo U1502 as it looks like this voltage is about 0V for most of the integration time. 

If I factor in the majority of the integration coming from U1500C, this charging current would be -4.52V/51kOhm = about -88uA

Bias current will change this, but we should be talking about hundreds of nA in the worst case, so this should not be a large source for error compared to our estimate. 

I calculate the voltage rise should be 8.313V, but you are seeing something more like 6.88V.

This disparity should be too large to be caused by Vos or by IIB. 

Can you use a larger value C1504?

I am interested to know if this error scales with cap value. 

Thanks,

Jacob

Hi Jacob,

Yes, I will check it tomorrow when I am back in the office.

Could you suggest a value for C1504 please?

Best regards,

Marius

Hey Marius,

Lets go with 220nF as a start. 

Thanks,

Jacob

Hello Jacob,

From what I observed a 220nF capacitor will make things worse. Please see below few oscilloscope plots.

Ch1: is U1500D output- pin14

Ch2: MOSFET drain current

Ch3: U1500C output - pin 8

Ch4: U1502A output -pin1

U1500D output switching period:

U1500D output voltage amplitude:

U1500C output voltage:

U1502 output voltage:

Best regards,

Marius

Hey Marius, 

Jacob is out of office on vacation, I will help support your application in the meantime.

What is the power supply on the LM6144? Is it still this power supply established a month ago? Or is this a different application?

Marius Pop said:

The V+ is connected at 12V and the V- is connected at -5.78V, so the Vcm range is 17.78V.

Please confirm. 

Thank you and warm regards, 
Carolina

Hi Carolina,

All LM6144/LM6142 have the V+ connected to 12V and the V- connected to -5.78V. I am using the LM614/LM6142 only in the DC Bias circuit that I designed for being able to control a low noise amplifier, and I am using the FDN337N MOSFET only to test my circuit.

Thank you for supporting me.

Marius

Hey Marius, 

Thank you for confirming the information. Although the TI analog circuit that Jacob provided is helpful, I think this tutorial on electronic tutorials is a little easier to grasp: Op-amp Integrator, Operational Amplifier Integrator

I recommend the following: 

• Implementing an RF so that the circuit may be biased properly at DC (which is the majority of your application since the target frequency is 30Hz). 
• Since the target frequency is 30Hz (0dB), we can work backwards to a decade before ~3Hz (+20dB) and a decade afterwards ~300Hz (-20dB). The target of fmax 100kHz is unrealistic.
  • If we do this, close to DC the gain will be -Rf/Rin = 20dB (-10V/V) -> If Rin = 10k, then Rf = 100k. 
  • Therefore Cf will be 1/(2*pi*Rin*fc)=530nF. 

Here is an excel I used: integrator.xlsx Feel free to change around the RIN value, this will affect all other values. 

If we do this, we expect the following: 

Notice how this is for an ideal op amp.

• With the gain of -10V/V, an input of 0 to 10V is too large for an op amp that is powered by +12V and -5V. The expected value is 100V and that is above the rail.
• Therefore the 0 to 10V input must be reduced down to not run into either the positive or negative rail when gained up by 10 V/V around mid-supply. 
• I think the way it is currently done is not correct, I recommend implementing a resistor divider to a buffer to the VG1 in my picture. 

All the best,
Carolina

Hello Carolina,

Thank you very much for your feedback.

Could you tell me please, did you try to simulate also by considering a MOSFET on the output of the opamp?

Idea is that I don't understand how to include a voltage divider and a buffer on the input of the opamp (at VG1 place in your simulation), because as you could see in the sketch that I provided above in one of the previous discussions, there are two signals that are coming at at the inverting input of the integrator opamp, Vout_U1500C and Vout_U1502A. U1500D is acting like an error amplifier, where the Vout_U1500C is the actual value of the DC bias current, and Vout_U1502A is the set value. Hence, could you help me please to understand how to change my circuit?

Thank you,

Marius

Hey Marius, 

I am back in office now.

Thanks for checking the 220nF.

It is safe to say that 220nF did not operate similar to the 100nF.

It looks like the 220nF interacted in an unintended way, causing the integrator output to rapidly saturate.

Did you use the 100k feedback resistor for any of  these measurements? 

The purpose of this 220nF measurement was to hopefully allow for an evaluation of the error disparity as a function of C1504 value. This would allow us to know if we are dealing with a resistive error, or something which varies with C1504 value. 

The MOSFET should not cause much output current to flow from the OPA, however it will act as a capacitive load due to the gate capacitance of the FET. R1507 should isolate this capacitance well enough to prevent issues due to excessive capacitive loading. You are welcome to check the U1500D output without this component populated on the board.  

Returning to the original problem, we are trying to understand why the slope of the integrator does not match your calculated values from the equation we discussed earlier, correct? I have LM614x samples in lab, I can test this circuit myself (with components to emulate the loading effects from the FET). 

There schematic is the most up to date, correct?

Thank you,

Jacob