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INA3221-Q1: I2C address

ziyang lai
Prodigy 150 points
Part Number: INA3221-Q1
Other Parts Discussed in Thread: INA4230, INA4235, INA3221

Tool/software:

hi TI expert, 

we meet a issue , that is we designe INA3221-Q1 I2C addr as 0X42 ( connect A0 to SDA), but sometimes we could not i2cscan 0x42 but 0x43(sometimes we can scan 0x42), do you have any suggestions about this issue? thanks.

  • 0
    Prodigy 150 points

    another question is ： What is the mechanism for identifying I2C addresse of this chip

  • 0 in reply to ziyang lai
    Guru 314780 points

    SDA and SCL are guaranteed to change during the start of an I²C transaction. The device samples the A0 pin at multiple times and detects these changes.

    It is possible that your I²C master does not conform to the setup/hold time limits in table 2, or that the SDA/SCL detection needs more time. Try using a slower I²C frequency.

  • 0
    TI__Mastermind 25425 points

    Hello Ziyang,

    In addition to what Clemens said, when connecting the SDA pin to A0 to set the device address, an additional hold time
    of 100 ns is needed on the MSB of the I2C address to ensure correct device addressing.

    Regards,

    Mitch

  • 0 in reply to Mitch M
    Prodigy 150 points

    HI Mitch

    what do you mean the hold time? the red circle one or green circle one in below picture?

    or the hold time of bit 6 & bit 7 ?

  • 0 in reply to ziyang lai
    TI__Mastermind 25425 points

    Hello Ziyang,

    The hold time I am referring to is the one in the green circle. As for the specific bit, bits 6 and 7 you highlighted are actually for the LSB of the address (A0), so the MSB would actually be bit 1 (on the far left in the second image you showed).

    Regards,

    Mitch

  • 0 in reply to Mitch M
    Prodigy 150 points

    hi Mitch, here is the result, switch frequency is 350 KHZ, it seems that the MSB hold time could not meet the 100ns requirement, do you have any idea?  lower the I2C frequency?

  • 0 in reply to ziyang lai
    TI__Mastermind 25425 points

    Hello Ziyang,

    There is probably a setting in your MCU somewhere that enables you to tune the timing of the communication to meet the timing requirements. If not, then it may be best to change the address to something other than SDA. If you slow down communication, then that may add more time and may work, but that depends on your MCU timing. 

    As a side note, you may be interested in our newer 4 channel devices, the INA4235 and INA4230. These devices have more address options (two address pins), and do not require extra hold time when using SDA as an address. These devices also have some additional features, such as energy monitoring. 

    Regards,

    Mitch

  • 0 in reply to Mitch M
    Prodigy 150 points

    hi Mitch

    thanks， it is strange a single case , other PCBA is OK, and we have changed another INA3221-Q1 on the fail PCBA, it still failed.  in our design, another INA3221 use  0x40, and some other device on the same I2C bus only support 0x41, so we have to set this INA3221 to 0X42 or 0x43.

    I think the newer current sense you mention it is not pin to pin to the INA3221,right?

  • 0 in reply to ziyang lai
    TI__Mastermind 25425 points

    Hey Ziyang,

    There is some tolerance in the devices, so it's possible your timing is right on the edge, and some devices may fail based on their individual variation. If you must use 0x42 or 0x43, then it may be best to just use 0x43, since the additional time is not needed with the address pin connected to SCL. 

    ziyang lai said:
    I think the newer current sense you mention it is not pin to pin to the INA3221,right?

    Correct, the newer devices are not pin-to-pin.

    Regards,

    Mitch

  • 0 in reply to Mitch M
    Prodigy 150 points

    OK ，thanks, we will try 0x43 . 

  • 0 in reply to Mitch M
    Prodigy 50 points

    Hi Mitch,

    Why the additional hold time is 100ns, can it be smaller? Is that an experience value or the must spec of the INA3221?

    In addition, Could you explain us how the A0 internal detection circuit works to define the I2C address? It may help us to avoid this issue in new design.

  • 0 in reply to Xiaochen Gao
    TI__Mastermind 25425 points

    Hello Xiaochen,

    The 100ns is a conservative time chosen to guarantee address identification. Although a smaller number may work, it would not be guaranteed. I am not sure the specific details of how the address detection works, but adding the 100ns is a safe way to avoid the issue. If you are starting a new design and are worried about this, then you may be interested in the newer INA4235 or INA4230, which do not require this additional hold time.

    Regards,

    Mitch 

  • 0 in reply to Mitch M
    Prodigy 50 points

    Hi Mitch,

    Not only the new design. I am worried that there may be more failed cases during quantity production.

    After changing the IIC pullup resistors from 2.2kohm to 4.7kohm, the previously failed case performed well during over 200 tests. However, the hold time waveform remained the same and tHD is still much less than 100ns, leaving me confused as to the root cause of the issue.

    Could you consult with other design engineers who may be familiar with the detection mechanism and inquire about this issue?Pray

    Thank you!

  • 0 in reply to Xiaochen Gao
    TI__Mastermind 25425 points

    Hello Xiaochen,

    I just discussed this more with my coworkers, and here are some more details for you.

    For the addressing, the INA samples the address pin to look for VS, GND, SDA, or SCL. To determine it is connected to SDA or SCL, it is looking for the transitions on those lines compared to the transition on the address pin. The additional hold time of 100ns is a conservative number to catch all devices, but each device will have it's own variation. So, some individual devices may not require the extra timing at all. It is important to note that the timing characteristics for a given device are not changing, so if you test it with a specific timing and it works, then it will continue to work at that timing. If you are right on the edge of timing, then with noise/jitter then a device may only connect sometimes, but you would likely still see that in your tests. In general it is best practice to just add the 100ns hold time to catch all possible cases, or just avoid using SDA as an address if you are unable to add the time. Either way, if you are testing the boards, then you should be able to see which ones are not working.

    As for changing your pullup resistors, that could have slowed the timing just enough to work for you, or it could have fixed an unrelated timing or logic level issue.

    Regards,

    Mitch