OPA2891: Clock Distribution for the ground based application system

I used the above scheme for the clock distribution section. How can i know the phase noise at  the each output. Does Tina supports for calculation of phase noise of OPA2891. Or suggest the tool to calculate the phase noise.

Why are you using an analog amplifier for a clock signal? Is it a square wave or a sine wave? At what voltage? (dBm does not describe a voltage.)

In general, I'd recommend a clock buffer like the CDCLVC1310 (which is for digital signals).

I choose OPA2891 as a buffer for clock distribution. The clock signal is sine wave having a power of 0 to 15dBm. Please recommend the scheme or IC to distribute the clock for sub-systems. The output should be constant 3dBm/5dBm whether if the signal level is in between 0 to 15dBm. 

Hi Srinadh Moka,

Thanks for sharing additional information. Unfortunately, we do not have phase noise calculation in TINA. However, we do have a test setup to measure and simulation that can be run to evaluate phase noise for the amplifier at specific clock frequency. I would need few inputs to narrow down on the amplifier

1. Is the output sine wave or square wave? We currently do not have any amplifier which gives constant output unrelated to input signal level. We can have a work around if it is limited fixed gain options that is needed.
2. If it is a gain is 1, then we have BUF802 which has excellent phase noise performance.
3. What is the available supply voltage?
4. Is the max frequency 10MHz?

Thanks
Vikas J

Hi Vikas,

Thanks for suggesting BUF802. Here is the some more clear information about the system.

1. The output's also sine wave. I have a requirement of total 8 outputs. 2 Outputs the levels should be the 3dB down to the input (for example if the input level is 13dBm then the 2 output levels should be 10dBm). 4 Outputs required to feed into the 4 individual Synthesizers RFFC2072 it accept the levels in between  -2dBm to 7dBm and remaining 2 outputs should maintain the minimum output levels are 5dBm. Suggest a best scheme to fulfill the requirement.

2. Can i use the BUF802 as protection at the input side. For suppose im reading more powered input signal then it won't effect to the entire system.

3. Maximum supply voltage is 5V and does parameters changes with respect to supply voltage.

4. Yes, the max frequency is 10MHz after there i generate the output by feeding 10MHz reference clock to the sub systems.

Thanks 

Srinadh

Hi Srinadh Moka,

I will reach out to you via email.

Thanks

Vikas J

Hi Vikas,

As you mentioned unfortunately there is no calculator for phase noise. In some browsers i seen the direct formula which converts from voltage noise to phase noise. I have attached the formula and conversions. Please check and confirm whether our consideration is correct or not.

In the datasheet there is a voltage noise frequency curve graph. Here the curve is at what particular frequency the response is given. Here the frequency means the change wrt input or what. 

Thanks, 

Srinadh

Hi Srinadh Moka,

The RMS Jitter formula from Phase Noise Power is correct. While the voltage noise graph and phase noise graph look similar, the main difference is that phase noise plot will have offset frequency and voltage noise has absolute frequency on x axis. Although, one of the main contributing factors for phase noise is the spot noise of the amplifier for given frequency, there are other factors like slew rate, GBW, flicker noise that affect phase noise. 
I could not find the source of the table above; it would be clearer if you could share the source for this table.

Thanks

Vikas J

please mention phase noise at  input 10Mhz Frequency.