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INA237: I²C Timing Requirement t_HDDAT

haya
Prodigy 20 points

Part Number: INA237

Tool/software:

Hi,

I have a question about the I²C timing requirements for the INA237, as specified in section 6.6 “Timing Requirements (I2C)” of the datasheet. The parameter t_HDDAT(Data hold time) is given as Min = 10 ns and Max = 900 ns. I’m not sure which of the following two interpretations is correct:

1.Slave-to-Master transfer: When the master reads from the INA237, the INA237 will update SDA at some point between 10 ns and 900 ns after the falling edge of SCL. Therefore, the master must sample the data before the slave’s update window.

2.Master-to-Slave transfer: When the master writes to the INA237, the master must drive SDA between 10 ns and 900 ns after the falling edge of SCL.

Which interpretation is correct? Any clarification would be greatly appreciated.

Thank you!

  • 0
    Guru 321680 points

    Electrically, there is no difference between masters and slaves. The clock signal is always generated by the master; the SDA line is sampled at the rising edge of SCL. In general, the device that is driving the SDA line changes the line at the falling edge of SCL to ensure that the setup/hold times are met.

  • 0
    TI__Mastermind 29325 points

    Hello Haya,

    In addition to what Clemens said, the 900ns Max is based on the 400kHz time. (Note how this value changes when in High-Speed Mode. Similarly if communicating slower than 400kHz, then you can have more time). Also, please note the below info about t_HDDAT from section 7.5.1 of the datasheet:

    Regards,

    Mitch

  • 0 in reply to Clemens Ladisch
    Prodigy 20 points

    Thank you for your response. I now understand that t_HDDAT applies both when the INA237 drives SDA and when the I²C master drives SDA.

  • +1 in reply to Mitch M
    Prodigy 20 points

    Thank you for your response.
    I now understand that the maximum t_HDDAT value (900 ns) is specified based on fast-mode (400 kHz).
    I have an additional question: when running the bus in standard-mode (100 kHz), can I assume that the t_HDDAT window will be roughly four times longer?
    My SCL waveform—while meeting the rise/fall-time requirements—is somewhat rounded, so I’d like to delay the master’s SDA transition as late as possible within that window.
    Also, since I’m not using the A0/A1 pins in this setup, I can disregard the address-pin hold requirement.

  • 0 in reply to haya
    TI__Mastermind 29325 points

    Hello Haya,

    haya said:
    when running the bus in standard-mode (100 kHz), can I assume that the t_HDDAT window will be roughly four times longer?

    Yes, that will be approximately the new window. 

    Regards,

    Mitch

  • 0 in reply to Mitch M
    Prodigy 20 points

    Hello Mitch,

    Thanks for your confirm. Now I know t_HDDAT window at 100 kHz become about four times longer. This answer solve my question. I will mark this thread as solved.

    Thank you again for your help!